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2022-04-22hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell1-5/+5
2022-04-22hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell5-6/+137
2022-04-22hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell3-25/+53
2022-04-22hw/intc/arm_gicv3: Implement new GICv4 redistributor registersPeter Maydell3-0/+99
2022-04-22hw/intc/arm_gicv3: Implement GICv4's new redistributor framePeter Maydell3-5/+26
2022-04-22hw/intc/arm_gicv3_its: Implement VINVALLPeter Maydell4-0/+45
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVIPeter Maydell4-0/+116
2022-04-22hw/intc/arm_gicv3_its: Implement INV for virtual interruptsPeter Maydell3-2/+31
2022-04-22hw/intc/arm_gicv3_its: Implement INV command properlyPeter Maydell4-2/+74
2022-04-22hw/intc/arm_gicv3_its: Implement VSYNCPeter Maydell3-0/+13
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVPPeter Maydell3-0/+85
2022-04-22hw/intc/arm_gicv3: Keep pointers to every connected ITSPeter Maydell3-0/+6
2022-04-22hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()Peter Maydell4-2/+125
2022-04-22hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt codePeter Maydell1-17/+32
2022-04-22hw/intc/arm_gicv3_its: Factor out CTE lookup sequencePeter Maydell1-70/+39
2022-04-22hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"Peter Maydell1-50/+54
2022-04-22hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUEPeter Maydell1-13/+16
2022-04-22hw/intc/arm_gicv3_its: Implement VMAPPPeter Maydell3-0/+102
2022-04-22hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTIPeter Maydell3-0/+102
2022-04-22hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4Peter Maydell2-0/+41
2022-04-22hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"Peter Maydell1-3/+7
2022-04-22hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell4-5/+16
2022-04-22hw/intc/arm_gicv3: Insist that redist region capacity matches CPU countPeter Maydell1-2/+2
2022-04-22hw/intc/arm_gicv3: Sanity-check num-cpu propertyPeter Maydell1-0/+4
2022-04-22hw/intc/arm_gicv3_its: Add missing blank linePeter Maydell1-0/+1
2022-04-22hw/intc: riscv_aclint: Add reset function of ACLINT devicesJim Shu1-0/+39
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang1-21/+50
2022-04-22hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINTFrank Chang1-15/+27
2022-04-22hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINTFrank Chang1-0/+4
2022-04-21Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson1-6/+3
2022-04-21intc/exynos4210_gic: replace snprintf() with g_strdup_printf()Marc-André Lureau1-6/+3
2022-04-21hw/arm/exynos4210: Put combiners into state structPeter Maydell1-30/+1
2022-04-21hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.cPeter Maydell1-77/+0
2022-04-21hw/arm/exynos4210: Put external GIC into state structPeter Maydell1-15/+2
2022-04-21hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.cPeter Maydell1-204/+0
2022-04-21hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]Peter Maydell1-1/+1
2022-04-21hw/arm/exynos4210: Coalesce board_irqs and irq_tablePeter Maydell1-24/+8
2022-04-21hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATEPeter Maydell1-107/+0
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-04-06Replace qemu_real_host_page variables with inlined functionsMarc-André Lureau1-1/+1
2022-03-25hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() loggingPeter Maydell1-2/+2
2022-03-21Use g_new() & friends where that makes obvious senseMarkus Armbruster2-4/+4
2022-03-18hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCGEric Auger2-3/+3
2022-03-14ppc/xive2: Make type Xive2EndSource not user creatableCédric Le Goater1-0/+1
2022-03-07hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace eventPeter Maydell1-1/+2
2022-03-07hw/intc/arm_gicv3: Fix missing spaces in error log messagesPeter Maydell2-4/+4
2022-03-07hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOpsPeter Maydell1-0/+8
2022-03-07hw/intc/arm_gicv3_its: Add trace events for table reads and writesPeter Maydell2-6/+40
2022-03-07hw/intc/arm_gicv3_its: Add trace events for commandsPeter Maydell2-2/+38
2022-03-03hw/intc: Add RISC-V AIA IMSIC device emulationAnup Patel3-0/+452
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