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2024-02-14apic, i386/tcg: add x2apic transitionsBui Quang Minh2-8/+67
This commit adds support for x2APIC transitions when writing to MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to TCG_EXT_FEATURES. The set_base in APICCommonClass now returns an integer to indicate error in execution. apic_set_base return -1 on invalid APIC state transition, accelerator can use this to raise appropriate exception. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14apic: add support for x2APIC modeBui Quang Minh2-68/+228
This commit extends the APIC ID to 32-bit long and remove the 255 max APIC ID limit in userspace APIC. The array that manages local APICs is now dynamically allocated based on the max APIC ID of created x86 machine. Also, new x2APIC IPI destination determination scheme, self IPI and x2APIC mode register access are supported. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-3-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14i386/tcg: implement x2APIC registers MSR accessBui Quang Minh2-32/+94
This commit creates apic_register_read/write which are used by both apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access. The apic_msr_read/write returns -1 on error, accelerator can use this to raise the appropriate exception. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-2-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-01-30hw/intc/xics: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
Include missing headers in order to avoid when refactoring unrelated headers: hw/intc/xics.c: In function 'icp_realize': hw/intc/xics.c:304:5: error: unknown type name 'PowerPCCPU' 304 | PowerPCCPU *cpu; | ^~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-11Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell2-154/+267
staging pull-loongarch-20240111 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZZ/QKgAKCRBAov/yOSY+ # 34eqBADA48++Z9gETFNheLUHdYEaja2emn+gSaoHLFquyq/l53w8RfrUII+BzV1o # T7D8xjlVQldAYZzqQn2pQe2S7r4ggfeNmxGxwJbCTW9sooGMwBnU8+Ix3ruSet7K # gI+UHLU4oHk6jdrT384tux2EG+qUmlLN1c7j4G/z1OzKEwFv7Q== # =+Pi0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 11 Jan 2024 11:25:30 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu: hw/intc/loongarch_extioi: Add vmstate post_load support hw/intc/loongarch_extioi: Add dynamic cpu number support hw/loongarch/virt: Set iocsr address space per-board rather than percpu hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops target/loongarch: Add loongarch kvm into meson build target/loongarch: Implement set vcpu intr for kvm target/loongarch: Restrict TCG-specific code target/loongarch: Implement kvm_arch_handle_exit target/loongarch: Implement kvm_arch_init_vcpu target/loongarch: Implement kvm_arch_init function target/loongarch: Implement kvm get/set registers target/loongarch: Supplement vcpu env initial when vcpu reset target/loongarch: Define some kvm_arch interfaces linux-headers: Synchronize linux headers from linux v6.7.0-rc8 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-11hw/intc/loongarch_extioi: Add vmstate post_load supportBibo Mao1-44/+76
There are elements sw_ipmap and sw_coremap, which is usd to speed up irq injection flow. They are saved and restored in vmstate during migration, indeed they can calculated from hw registers. Here post_load is added for get sw_ipmap and sw_coremap from extioi hw state. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/intc/loongarch_extioi: Add dynamic cpu number supportBibo Mao1-36/+71
On LoongArch physical machine, one extioi interrupt controller only supports 4 cpus. With processor more than 4 cpus, there are multiple extioi interrupt controllers; if interrupts need to be routed to other cpus, they are forwarded from extioi node0 to other extioi nodes. On virt machine model, there is simple extioi interrupt device model. All cpus can access register of extioi interrupt controller, however interrupt can only be route to 4 vcpu for compatible with old kernel. This patch adds dynamic cpu number support about extioi interrupt. With old kernel legacy extioi model is used, however kernel can detect and choose new route method in future, so that interrupt can be routed to all vcpus. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/loongarch/virt: Set iocsr address space per-board rather than percpuBibo Mao2-18/+46
LoongArch system has iocsr address space, most iocsr registers are per-board, however some iocsr register spaces banked for percpu such as ipi mailbox and extioi interrupt status. For banked iocsr space, each cpu has the same iocsr space, but separate data. This patch changes iocsr address space per-board rather percpu, for iocsr registers specified for cpu, MemTxAttrs.requester_id can be parsed for the cpu. With this patches, the total address space on board will be simple, only iocsr address space and system memory, rather than the number of cpu and system memory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi opsBibo Mao1-59/+77
There are two interface pairs for MemoryRegionOps, read/write and read_with_attrs/write_with_attrs. The later is better for ipi device emulation since initial cpu can be parsed from attrs.requester_id. And requester_id can be overrided for IOCSR_IPI_SEND and mail_send function when it is to forward message to another vcpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-09hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registersPeter Maydell1-0/+11
Mark up the cpreginfo structs for the GIC CPU registers to indicate the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
2024-01-09hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registersPeter Maydell1-4/+13
The hypervisor can deliver (virtual) LPIs to a guest by setting up a list register to have an intid which is an LPI. The GIC has to treat these a little differently to standard interrupt IDs, because LPIs have no Active state, and so the guest will only EOI them, it will not also deactivate them. So icv_eoir_write() must do two things: * if the LPI ID is not in any list register, we drop the priority but do not increment the EOI count * if the LPI ID is in a list register, we immediately deactivate it, regardless of the split-drop-and-deactivate control This can be seen in the VirtualWriteEOIR0() and VirtualWriteEOIR1() pseudocode in the GICv3 architecture specification. Without this fix, potentially a hypervisor guest might stall because LPIs get stuck in a bogus Active+Pending state. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
2024-01-09hw/intc/armv7m_nvic: add "num-prio-bits" propertySamuel Tardieu1-1/+22
Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits. This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless a SOC specifies the number of bits to use, the previous behavior is maintained for backward compatibility. Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240106181503.1746200-2-sam@rfc1149.net Suggested-by: Anton Kochkov <anton.kochkov@proton.me> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-08system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi2-10/+10
The Big QEMU Lock (BQL) has many names and they are confusing. The actual QemuMutex variable is called qemu_global_mutex but it's commonly referred to as the BQL in discussions and some code comments. The locking APIs, however, are called qemu_mutex_lock_iothread() and qemu_mutex_unlock_iothread(). The "iothread" name is historic and comes from when the main thread was split into into KVM vcpu threads and the "iothread" (now called the main loop thread). I have contributed to the confusion myself by introducing a separate --object iothread, a separate concept unrelated to the BQL. The "iothread" name is no longer appropriate for the BQL. Rename the locking APIs to: - void bql_lock(void) - void bql_unlock(void) - bool bql_locked(void) There are more APIs with "iothread" in their names. Subsequent patches will rename them. There are also comments and documentation that will be updated in later patches. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Acked-by: Fabiano Rosas <farosas@suse.de> Acked-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Peter Xu <peterx@redhat.com> Acked-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Acked-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-id: 20240102153529.486531-2-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-12-29hw/intc: Constify VMStateRichard Henderson38-77/+77
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-35-richard.henderson@linaro.org>
2023-12-19hw/intc/arm_gicv3: Include missing 'qemu/error-report.h' headerPhilippe Mathieu-Daudé1-0/+1
kvm_arm_its_reset_hold() calls warn_report(), itself declared in "qemu/error-report.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231123183518.64569-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-20hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZBen Dooks1-2/+2
The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from ic{c,v}_fullprio_mask should technically also remove any bit above 7 as these are marked reserved (read 0) and should therefore should not be written as anything other than 0. This was noted during a run of a proprietary test system and discused on the mailing list [1] and initially thought not to be an issue due to RES0 being technically allowed to be written to and read back as long as the implementation does not use the RES0 bits. It is very possible that the values are used in comparison without masking, as pointed out by Peter in [2], if (cs->hppi.prio >= cs->icc_pmr_el1) may well do the wrong thing. Masking these values in ic{c,v}_fullprio_mask() should fix this and prevent any future problems with playing with the values. [1]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00607.html [2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Message-id: 20231116172818.792364-1-ben.dooks@codethink.co.uk Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-11-03Merge tag 'migration-20231102-pull-request' of ↵Stefan Hajnoczi1-2/+16
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request (20231102) Hi In this pull request: - migration reboot mode (steve) * I disabled the test because our CI don't like programs using so much shared memory. Searching for a fix. - test for postcopy recover (fabiano) - MigrateAddress QAPI (het) - better return path error handling (peter) - traces for downtime (peter) - vmstate_register() check for duplicates (juan) thomas find better solutions for s390x and ipmi. now also works on s390x Please, apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmVDipMACgkQ9IfvGFhy # 1yNYnQ/9E5Cywsoqljqa/9FiKBSII2qMrmkfu6JLKqePnsh5pFZiukbudYRuJCCe # ZTDEmD0NmKRJbDx2xRU1qx/e6gKJy+gz37KP89Buuh/WwZHPboPYtxQpGvCSiH26 # J3i+1+TgaqmkLzcO35wa8tp6gneQclWeAwKgMvdb4cm2pJEhgWRKI62ccyLzxeve # UCzFQn60t55ETyVZGnRD4YwdTQvGKH+DPlyTuJOLR3DePuvZd8EdH+ypvB4RLAy7 # 3+CuQOxmF5LRXPbpJuAeOsudbmhhHzrO/yL7ZmsiKQTthsJv+SzC1bO94jhQrawZ # Q7GCii5KpGq0KnRTRKZRGk6XKwxcYRduXMX3R5tXuVmDmCZsjhXzziU8yEdftph8 # 5TJdk1o0Gb043EFu81mrsQYS+9yJqe6sy6m3PTJaec54cAty5ln+c17WOvpAOaSV # +1phe05ftuVPmQ3KWhbIR/tCmavNLwEZxpVIfyaKJx04bFbtQ9gRpRyURORX4KXc # s4WXvNirQEohxYBnP4TPvA09xBTW3V08pk/wRDwt0YDXnLiqCltOuxD8r05K8K4B # MkCLcWj0g7he2tBkF60oz1KSIE0oTB81um9AzLIv5F2YSYLaJM5BIcoC437MR2f4 # MOR7drR1fP5GsRu/SeU5BWvhVq3IvdOxR7G2MLNRJJvl7ZtGXDc= # =uaqL # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Nov 2023 19:40:03 HKT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20231102-pull-request' of https://gitlab.com/juan.quintela/qemu: (40 commits) migration: modify test_multifd_tcp_none() to use new QAPI syntax. migration: Implement MigrateChannelList to hmp migration flow. migration: Implement MigrateChannelList to qmp migration flow. migration: modify migration_channels_and_uri_compatible() for new QAPI syntax migration: New migrate and migrate-incoming argument 'channels' migration: Convert the file backend to the new QAPI syntax migration: convert exec backend to accept MigrateAddress. migration: convert rdma backend to accept MigrateAddress migration: convert socket backend to accept MigrateAddress migration: convert migration 'uri' into 'MigrateAddress' migration: New QAPI type 'MigrateAddress' migration: Change ram_dirty_bitmap_reload() retval to bool tests/migration-test: Add a test for postcopy hangs during RECOVER migration: Allow network to fail even during recovery migration: Refactor error handling in source return path tests/qtest: migration: add reboot mode test cpr: reboot mode cpr: relax vhost migration blockers cpr: relax blockdev migration blockers migration: per-mode blockers ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-01migration: Hack to maintain backwards compatibility for ppcJuan Quintela1-2/+16
Current code does: - register pre_2_10_vmstate_dummy_icp with "icp/server" and instance dependinfg on cpu number - for newer machines, it register vmstate_icp with "icp/server" name and instance 0 - now it unregisters "icp/server" for the 1st instance. This is wrong at many levels: - we shouldn't have two VMSTATEDescriptions with the same name - In case this is the only solution that we can came with, it needs to be: * register pre_2_10_vmstate_dummy_icp * unregister pre_2_10_vmstate_dummy_icp * register real vmstate_icp Created vmstate_replace_hack_for_ppc() with warnings left and right that it is a hack. CC: Cedric Le Goater <clg@kaod.org> CC: Daniel Henrique Barboza <danielhb413@gmail.com> CC: David Gibson <david@gibson.dropbear.id.au> CC: Greg Kurz <groug@kaod.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231020090731.28701-8-quintela@redhat.com>
2023-11-01hw/m68k/irqc: Pass CPU using QOM link propertyPhilippe Mathieu-Daudé1-1/+9
Avoid the interrupt controller directly access the 'first_cpu' global. Pass 'cpu' from the board code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231024083010.12453-2-philmd@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2023-10-27target/arm: Move feature test functions to their own headerPeter Maydell1-0/+1
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
2023-10-25kvm: require KVM_IRQFD for kernel irqchipPaolo Bonzini1-1/+1
KVM_IRQFD was introduced in Linux 2.6.32, and since then it has always been available on architectures that support an in-kernel interrupt controller. We can require it unconditionally. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_CAP_SIGNAL_MSIPaolo Bonzini1-2/+1
This was introduced in KVM in Linux 3.5, we can require it unconditionally in kvm_irqchip_send_msi(). However, not all architectures have to implement it so check it only in x86, the only architecture that ever had MSI injection but not KVM_CAP_SIGNAL_MSI. ARM uses it to detect the presence of the ITS emulation in the kernel, introduced in Linux 4.8. Assume that it's there and possibly fail when realizing the arm-its-kvm device. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-20Merge tag 'migration-20231020-pull-request' of ↵Stefan Hajnoczi3-6/+3
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request (20231020) In this pull request: - disable analyze-migration on s390x (thomas) - Fix parse_ramblock() (peter) - start merging live update (steve) - migration-test support for using several binaries (fabiano) - multifd cleanups (fabiano) CI: https://gitlab.com/juan.quintela/qemu/-/pipelines/1042492801 Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmUyJMsACgkQ9IfvGFhy # 1yP0AQ/9ELr6VJ0crqzfGm2dy2emnZMaQhDtzR4Kk4ciZF6U+GiATdGN9hK499mP # 6WzRIjtSzwD8YZvhLfegxIVTGcEttaM93uXFPznWrk7gwny6QTvuA4qtcRYejTSl # wE4GQQOsSrukVCUlqcZtY/t2aphVWQzlx8RRJE3XGaodT1gNLMjd+xp34NbbOoR3 # 32ixpSPUCOGvCd7hb+HG7pEzk+905Pn2URvbdiP71uqhgJZdjMAv8ehSGD3kufdg # FMrZyIEq7Eguk2bO1+7ZiVuIafXXRloIVqi1ENmjIyNDa/Rlv2CA85u0CfgeP6qY # Ttj+MZaz8PIhf97IJEILFn+NDXYgsGqEFl//uNbLuTeCpmr9NPhBzLw8CvCefPrR # rwBs3J+QbDHWX9EYjk6QZ9QfYJy/DXkl0KfdNtQy9Wf+0o1mHDn5/y3s782T24aJ # lGo0ph4VJLBNOx58rpgmoO5prRIjqzF5w4j8pCSeGUC4Bcub5af4TufYrwaf+cps # iIbNFx79dLXBlfkKIn7i9RLpz7641Fs/iTQ/MZh1eyvX++UDXAPWnbd4GDYOEewA # U3WKsTs/ipIbY8nqaO4j1VMzADPUfetBXznBw60xsZcfjynFJsPV6/F/0OpUupdv # qPEY4LZ2uwP4K7AlzrUzUn2f3BKrspL0ObX0qTn0WJ8WX5Jp/YA= # =m+uB # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 23:57:15 PDT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20231020-pull-request' of https://gitlab.com/juan.quintela/qemu: tests/qtest: Don't print messages from query instances tests/qtest/migration: Allow user to specify a machine type tests/qtest/migration: Support more than one QEMU binary tests/qtest/migration: Set q35 as the default machine for x86_86 tests/qtest/migration: Specify the geometry of the bootsector tests/qtest/migration: Define a machine for all architectures tests/qtest/migration: Introduce find_common_machine_version tests/qtest: Introduce qtest_resolve_machine_alias tests/qtest: Introduce qtest_has_machine_with_env tests/qtest: Allow qtest_get_machines to use an alternate QEMU binary tests/qtest: Introduce qtest_init_with_env tests/qtest: Allow qtest_qemu_binary to use a custom environment variable migration/multifd: Stop checking p->quit in multifd_send_thread migration: simplify notifiers migration: Fix parse_ramblock() on overwritten retvals migration: simplify blockers tests/qtest/migration-test: Disable the analyze-migration.py test on s390x Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20migration: simplify blockersSteve Sistare3-6/+3
Modify migrate_add_blocker and migrate_del_blocker to take an Error ** reason. This allows migration to own the Error object, so that if an error occurs in migrate_add_blocker, migration code can free the Error and clear the client handle, simplifying client code. It also simplifies the migrate_del_blocker call site. In addition, this is a pre-requisite for a proposed future patch that would add a mode argument to migration requests to support live update, and maintain a list of blockers for each mode. A blocker may apply to a single mode or to multiple modes, and passing Error** will allow one Error object to be registered for multiple modes. No functional change. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Tested-by: Michael Galaxy <mgalaxy@akamai.com> Reviewed-by: Michael Galaxy <mgalaxy@akamai.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <1697634216-84215-1-git-send-email-steven.sistare@oracle.com>
2023-10-19hw/intc/spapr_xive: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-6/+6
There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Transformation done using the following coccinelle script: @@ expression sbdev; expression index; expression addr; expression subregion; @@ - sysbus_init_mmio(sbdev, subregion); ... when != sbdev - sysbus_mmio_map(sbdev, index, addr); + memory_region_add_subregion(get_system_memory(), addr, subregion); Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-8-philmd@linaro.org>
2023-10-19hw/intc/spapr_xive: Move sysbus_init_mmio() calls aroundPhilippe Mathieu-Daudé1-3/+3
In order to make the next commit trivial, move sysbus_init_mmio() calls just before the corresponding sysbus_mmio_map() calls. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231019131647.19690-7-philmd@linaro.org>
2023-10-19hw/intc/apic: Use ERRP_GUARD() in apic_common_realize()Philippe Mathieu-Daudé1-0/+4
APICCommonClass::realize() is a DeviceRealize() handler which take an Error** parameter and can fail. Do not proceed further on failure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <20231003082728.83496-2-philmd@linaro.org>
2023-10-12target/riscv: move KVM only files to kvm subdirDaniel Henrique Barboza1-1/+1
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg. Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson3-8/+8
Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-29hw/intc/arm_gicv3_its: Avoid shadowing variable in do_process_its_cmd()Peter Maydell1-3/+3
Avoid shadowing a local variable in do_process_its_cmd(): ../../hw/intc/arm_gicv3_its.c:548:17: warning: declaration of ‘ite’ shadows a previous local [-Wshadow=compatible-local] 548 | ITEntry ite = {}; | ^~~ ../../hw/intc/arm_gicv3_its.c:518:13: note: shadowed declaration is here 518 | ITEntry ite; | ^~~ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20230922152944.3583438-2-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2023-09-29hw/intc/openpic: Clean up local variable shadowingPhilippe Mathieu-Daudé1-5/+2
Fix: hw/intc/openpic.c: In function ‘openpic_gbl_write’: hw/intc/openpic.c:614:17: warning: declaration of ‘idx’ shadows a previous local [-Wshadow=compatible-local] 614 | int idx; | ^~~ hw/intc/openpic.c:568:9: note: shadowed declaration is here 568 | int idx; | ^~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230904162824.85385-3-philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2023-09-21hw/other: spelling fixesMichael Tokarev8-12/+12
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18ppc/xive: Fix uint32_t overflowCédric Le Goater1-1/+1
As reported by Coverity, "idx << xive->pc_shift" is evaluated using 32-bit arithmetic, and then used in a context expecting a "uint64_t". Add a uint64_t cast. Fixes: Coverity CID 1519049 Fixes: b68147b7a5bf ("ppc/xive: Add support for the PC MMIOs") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230914154650.222111-1-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-09-11Merge tag 'pull-riscv-to-apply-20230911' of ↵Stefan Hajnoczi3-25/+63
https://github.com/alistair23/qemu into staging First RISC-V PR for 8.2 * Remove 'host' CPU from TCG * riscv_htif Fixup printing on big endian hosts * Add zmmul isa string * Add smepmp isa string * Fix page_check_range use in fault-only-first * Use existing lookup tables for MixColumns * Add RISC-V vector cryptographic instruction set support * Implement WARL behaviour for mcountinhibit/mcounteren * Add Zihintntl extension ISA string to DTS * Fix zfa fleq.d and fltq.d * Fix upper/lower mtime write calculation * Make rtc variable names consistent * Use abi type for linux-user target_ucontext * Add RISC-V KVM AIA Support * Fix riscv,pmu DT node path in the virt machine * Update CSR bits name for svadu extension * Mark zicond non-experimental * Fix satp_mode_finalize() when satp_mode.supported = 0 * Fix non-KVM --enable-debug build * Add new extensions to hwprobe * Use accelerated helper for AES64KS1I * Allocate itrigger timers only once * Respect mseccfg.RLB for pmpaddrX changes * Align the AIA model to v1.0 ratified spec * Don't read the CSR in riscv_csrrw_do64 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmT+ttMACgkQr3yVEwxT # gBN/rg/+KhOvL9xWSNb8pzlIsMQHLvndno0Sq5b9Rb/o5z1ekyYfyg6712N3JJpA # TIfZzOIW7oYZV8gHyaBtOt8kIbrjwzGB2rpCh4blhm+yNZv7Ym9Ko6AVVzoUDo7k # 2dWkLnC+52/l3SXGeyYMJOlgUUsQMwjD6ykDEr42P6DfVord34fpTH7ftwSasO9K # 35qJQqhUCgB3fMzjKTYICN6Rm1UluijTjRNXUZXC0XZlr+UKw2jT/UsybbWVXyNs # SmkRtF1MEVGvw+b8XOgA/nG1qVCWglTMcPvKjWMY+cY9WLM6/R9nXAV8OL/JPead # v1LvROJNukfjNtDW6AOl5/svOJTRLbIrV5EO7Hlm1E4kftGmE5C+AKZZ/VT4ucUK # XgqaHoXh26tFEymVjzbtyFnUHNv0zLuGelTnmc5Ps1byLSe4lT0dBaJy6Zizg0LE # DpTR7s3LpyV3qB96Xf9bOMaTPsekUjD3dQI/3X634r36+YovRXapJDEDacN9whbU # BSZc20NoM5UxVXFTbELQXolue/X2BRLxpzB+BDG8/cpu/MPgcCNiOZaVrr/pOo33 # 6rwwrBhLSCfYAXnJ52qTUEBz0Z/FnRPza8AU/uuRYRFk6JhUXIonmO6xkzsoNKuN # QNnih/v1J+1XqUyyT2InOoAiTotzHiWgKZKaMfAhomt2j/slz+A= # =aqcx # -----END PGP SIGNATURE----- # gpg: Signature made Mon 11 Sep 2023 02:42:27 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qemu: (45 commits) target/riscv: don't read CSR in riscv_csrrw_do64 target/riscv: Align the AIA model to v1.0 ratified spec target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes target/riscv: Allocate itrigger timers only once target/riscv: Use accelerated helper for AES64KS1I linux-user/riscv: Add new extensions to hwprobe hw/intc/riscv_aplic.c fix non-KVM --enable-debug build hw/riscv/virt.c: fix non-KVM --enable-debug build riscv: zicond: make non-experimental target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 target/riscv: Update CSR bits name for svadu extension hw/riscv: virt: Fix riscv,pmu DT node path target/riscv: select KVM AIA in riscv virt machine target/riscv: update APLIC and IMSIC to support KVM AIA target/riscv: Create an KVM AIA irqchip target/riscv: check the in-kernel irqchip support target/riscv: support the AIA device emulation with KVM enabled linux-user/riscv: Use abi type for target_ucontext hw/intc: Make rtc variable names consistent hw/intc: Fix upper/lower mtime write calculation ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-09-11hw/intc/riscv_aplic.c fix non-KVM --enable-debug buildDaniel Henrique Barboza1-6/+2
Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM environment with the following error: /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function `riscv_kvm_aplic_request': ./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq' collect2: error: ld returned 1 exit status This happens because the debug build will poke into the 'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to the KVM only function riscv_kvm_aplic_request(). There are multiple solutions to fix this. We'll go with the same solution from the previous patch, i.e. add a kvm_enabled() conditional to filter out the block. But there's a catch: riscv_kvm_aplic_request() is a local function that would end up being used if the compiler crops the block, and this won't work. Quoting Richard Henderson's explanation in [1]: "(...) the compiler won't eliminate entire unused functions with -O0" We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its declaration in kvm_riscv.h, where all other KVM specific public functions are already declared. Other archs handles KVM specific code in this manner and we expect to do the same from now on. [1] https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/ Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11target/riscv: update APLIC and IMSIC to support KVM AIAYong-Xuan Wang2-20/+61
KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed, APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the mmio operations of APLIC when using KVM AIA and send wired interrupt signal via KVM_IRQ_LINE API. After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11hw/intc: Make rtc variable names consistentJason Chien1-3/+3
The variables whose values are given by cpu_riscv_read_rtc() should be named "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() should be named "rtc_r". Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230728082502.26439-2-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11hw/intc: Fix upper/lower mtime write calculationJason Chien1-2/+3
When writing the upper mtime, we should keep the original lower mtime whose value is given by cpu_riscv_read_rtc() instead of cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime. Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230728082502.26439-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-08hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()Philippe Mathieu-Daudé1-9/+6
Fix when using GCC v11.4 (Ubuntu 11.4.0-1ubuntu1~22.04) with CFLAGS=-Og: [4/6] Compiling C object libcommon.fa.p/hw_intc_arm_gicv3_its.c.o FAILED: libcommon.fa.p/hw_intc_arm_gicv3_its.c.o inlined from ‘lookup_vte’ at hw/intc/arm_gicv3_its.c:453:9, inlined from ‘vmovp_callback’ at hw/intc/arm_gicv3_its.c:1039:14: hw/intc/arm_gicv3_its.c:347:9: error: ‘vte.rdbase’ may be used uninitialized [-Werror=maybe-uninitialized] 347 | trace_gicv3_its_vte_read(vpeid, vte->valid, vte->vptsize, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 348 | vte->vptaddr, vte->rdbase); | ~~~~~~~~~~~~~~~~~~~~~~~~~~ hw/intc/arm_gicv3_its.c: In function ‘vmovp_callback’: hw/intc/arm_gicv3_its.c:1036:13: note: ‘vte’ declared here 1036 | VTEntry vte; | ^~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230831131348.69032-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-06ppc/xive: Add support for the PC MMIOsCédric Le Goater1-36/+48
The XIVE interrupt contoller maintains various fields on interrupt targets in a structure called NVT. Each unit has a NVT cache, backed by RAM. When the NVT structure is not local (in RAM) to the chip, the XIVE interrupt controller forwards the memory operation to the owning chip using the PC MMIO region configured for this purpose. QEMU does not need to be so precise since software shouldn't perform any of these operations. The model implementation is simplified to return the RAM address of the NVT structure which is then used by pnv_xive_vst_write or read to perform the operation in RAM. Remove the last use of pnv_xive_get_remote(). Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06ppc/xive: Handle END triggers between chips with MMIOsCédric Le Goater2-2/+68
The notify page of the interrupt controller can either be used to receive trigger events from the HW controllers (PHB, PSI) or to reroute interrupts between Interrupt Controllers. In which case, the VSD table is used to determine the address of the notify page of the remote IC and the store data is forwarded. Today, our model grabs the remote VSD (EAS, END, NVT) address using pnv_xive_get_remote() helper. Be more precise and implement remote END triggers using a store on the remote IC notify page. We still have a shortcut in the model for the NVT accesses which we will address later. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06ppc/xive: Introduce a new XiveRouter end_notify() handlerCédric Le Goater1-10/+18
It will help us model the END triggers on the PowerNV machine, which can be rerouted to another interrupt controller. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06ppc/xive: Use address_space routines to access the machine RAMCédric Le Goater2-8/+46
to log an error in case of bad configuration of the XIVE tables by the FW. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-08-31accel: Remove HAX acceleratorPhilippe Mathieu-Daudé1-2/+1
HAX is deprecated since commits 73741fda6c ("MAINTAINERS: Abort HAXM maintenance") and 90c167a1da ("docs/about/deprecated: Mark HAXM in QEMU as deprecated"), released in v8.0.0. Per the latest HAXM release (v7.8 [*]), the latest QEMU supported is v7.2: Note: Up to this release, HAXM supports QEMU from 2.9.0 to 7.2.0. The next commit (https://github.com/intel/haxm/commit/da1b8ec072) added: HAXM v7.8.0 is our last release and we will not accept pull requests or respond to issues after this. It became very hard to build and test HAXM. Its previous maintainers made it clear they won't help. It doesn't seem to be a very good use of QEMU maintainers to spend their time in a dead project. Save our time by removing this orphan zombie code. [*] https://github.com/intel/haxm/releases/tag/v7.8.0 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230831082016.60885-1-philmd@linaro.org>
2023-08-24hw/intc/loongarch_pch: fix edge triggered irq handlingBibo Mao1-1/+6
For edge triggered irq, qemu_irq_pulse is used to inject irq. It will set irq with high level and low level soon to simluate pulse irq. For edge triggered irq, irq is injected and set as pending at rising level, do not clear irq at lowering level. LoongArch pch interrupt will clear irq for lowering level irq, there will be problem. ACPI ged deivce is edge-triggered irq, it is used for cpu/memory hotplug. This patch fixes memory hotplug issue on LoongArch virt machine. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230707091557.1474790-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-07-25arm: spelling fixesMichael Tokarev3-4/+4
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-25s390x: spelling fixesMichael Tokarev1-1/+1
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-07-18s390x: Fix QEMU abort by selecting S390_FLIC_KVMCédric Le Goater1-1/+0
If QEMU is built with --without-default-devices, the s390-flic-kvm device is missing and QEMU aborts when started with the KVM accelerator. Make sure it's available by selecting S390_FLIC_KVM in Kconfig. Consequently, this also fixes an abort in tests/qtest/migration-test. Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20230711151440.716822-1-clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-07-07pnv/xive2: Always pass a presenter object when accessing the TIMAFrederic Barrat1-2/+4
The low-level functions to access the TIMA take a presenter object as a first argument. When accessing the TIMA from the IC BAR, i.e. indirect calls, we currently pass a NULL pointer for the presenter argument. While it appears ok with the current usage, it's dangerous. And it's pretty easy to figure out the presenter in that context, so this patch fixes it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230705081400.218408-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Print CPU target in all TIMA tracesFrederic Barrat2-4/+4
Add the CPU target in the trace when reading/writing the TIMA space. It was already done for other TIMA ops (notify, accept, ...), only missing for those 2. Useful for debug and even more now that we experiment with SMT. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230705110039.231148-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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