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2013-11-05realview_gic: Prepare for QOM embeddingAndreas Färber1-14/+1
Move state struct, type constant and cast macro to a new header. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05realview_gic: Convert to QOM realizeAndreas Färber1-16/+35
Embed GICState and replace SysBus initfn with realizefn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm_gic: Extract headers hw/intc/arm_gic{,_common}.hAndreas Färber2-87/+11
Rename NCPU to GIC_NCPU and move GICState away from gic_internal.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-10-25xics-kvm: enable irqfd for MSIAlexey Kardashevskiy1-0/+6
This enables IRQFD support for sPAPR. The feature decreases the latency of interrupt handling. To enable IRQFD for MSI, this sets kvm_gsi_direct_mapping to true which enables direct MSI mapping. To enable IRQFD for LSI (level triggered INTx interrupts), a PCI host bus callback is required. The patch for that is coming next. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: Implement H_XIRR_XBenjamin Herrenschmidt1-0/+14
This implements H_XIRR_X hypercall in addition to H_XIRR as it is mandatory for PAPR+ and there is no way for the guest to detect whether it is supported or not so just add it. As the Partition Adjunct Option is not supported at the moment, the CPPR parameter of the hypercall is ignored. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: Implement H_IPOLLBenjamin Herrenschmidt1-0/+13
This adds support for the H_IPOLL hypercall which the guest uses to poll for a pending interrupt. This hypercall is mandatory for PAPR+ and there is no way for the guest to detect whether it is supported or not so just add it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics-kvm: Support for in-kernel XICS interrupt controllerDavid Gibson2-0/+489
Recent (host) kernels support emulating the PAPR defined "XICS" interrupt controller system within KVM. This patch allows qemu to initialize and configure the in-kernel XICS, and keep its state in sync with qemu's XICS state as necessary. This should give considerable performance improvements. e.g. on a simple IPI ping-pong test between hardware threads, using qemu XICS gives us around 5,000 irqs/second, whereas the in-kernel XICS gives us around 70,000 irqs/s on the same hardware configuration. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [Mike Qiu <qiudayu@linux.vnet.ibm.com>: fixed mistype which caused ics_set_kvm_state() to fail] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: add cpu_setup callbackAlexey Kardashevskiy1-0/+5
This adds a cpu_setup callback to the XICS device class (as XICS-KVM will do it different), xics_cpu_setup() will call it if it is set. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: split to xics and xics-commonAlexey Kardashevskiy1-20/+136
The upcoming XICS-KVM support will use bits of emulated XICS code. So this introduces new level of hierarchy - "xics-common" class. Both emulated XICS and XICS-KVM will inherit from it and override class callbacks when required. The new "xics-common" class implements: 1. replaces static "nr_irqs" and "nr_servers" properties with the dynamic ones and adds callbacks to be executed when properties are set. 2. xics_cpu_setup() callback renamed to xics_common_cpu_setup() as it is a common part for both XICS'es 3. xics_reset() renamed to xics_common_reset() for the same reason. The emulated XICS changes: 1. the part of xics_realize() which creates ICPs is moved to the "nr_servers" property callback as realize() is too late to create/initialize devices and instance_init() is too early to create devices as the number of child devices comes via the "nr_servers" property. 2. added ics_initfn() which does a little part of what xics_realize() did. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: add missing const specifiers to TypeInfoAlexey Kardashevskiy1-2/+2
This adds missing const specifiers to ICS and ICP TypeInfo's. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: convert init() to realize()Alexey Kardashevskiy1-6/+22
This fixes XICS according new QOM rules. This converts ICS's init() callbacks to realize(). This converts legacy qdev_init_nofail() to property_set(realized). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: add pre_save/post_load dispatchersAlexey Kardashevskiy1-3/+53
The upcoming support of in-kernel XICS will redefine migration callbacks for both ICS and ICP so classes and callback pointers are added. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: replace fprintf with error_reportAlexey Kardashevskiy1-2/+3
This replaces old-style fprintf with new style error_report. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: move reset and cpu_setupAlexey Kardashevskiy1-36/+36
This simple change makes following patches nicer. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-09-03Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into ↵Anthony Liguori1-1/+1
staging QOM device refactorings * Fix QOM and ISA documentation errors * Extend object_initialize() et al. to check the instance size # gpg: Signature made Fri 30 Aug 2013 02:19:48 PM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (14) and others # Via Andreas Färber * afaerber/tags/qom-devices-for-anthony: isa: Fix documentation of isa_register_portio_list() qom: Assert instance size in object_initialize_with_type() qom: Pass available size to object_initialize() qdev: Pass size to qbus_create_inplace() virtio-mmio: Pass size to virtio_mmio_bus_new() virtio-ccw: Pass size to virtio_ccw_bus_new() s390-virtio-bus: Pass size to virtio_s390_bus_new() virtio-pci: Pass size to virtio_pci_bus_new() usb: Pass size to usb_bus_new() scsi: Pass size to scsi_bus_new() pci: Pass size to pci_bus_new_inplace() ide: Pass size to ide_bus_new() ipack: Pass size to ipack_bus_new_inplace() intel-hda: Pass size to hda_codec_bus_init() qom: Fix object_initialize_with_type() argument name in documentation virtio: Remove unnecessary OBJECT() casts object: Fix typo in qom/object.h
2013-09-02xics: move registration of global state to realize()Alexey Kardashevskiy1-10/+11
Registration of global state belongs into realize so move it there. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-08-30qom: Pass available size to object_initialize()Andreas Färber1-1/+1
To be passed on to object_initialize_with_type(). Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (virtio-ccw) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh4-19/+19
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-29ioapic: QOM cast cleanupAndreas Färber1-1/+1
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29xilinx_intc: QOM cast cleanupAndreas Färber1-7/+12
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29slavio_intctl: QOM cast cleanupAndreas Färber1-17/+18
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29realview_gic: QOM cast cleanupAndreas Färber1-7/+13
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29puv3_intc: QOM cast cleanupAndreas Färber1-9/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pl190: QOM cast cleanupAndreas Färber1-18/+22
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pl190: Rename pl190_state to PL190StateAndreas Färber1-21/+21
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29omap_intc: QOM'ify omap-intc and omap2-intcAndreas Färber1-22/+35
Create a new abstract base type and let omap-intc and omap2-intc inherit from it. Introduce a type constant and use QOM casts. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29lm32_pic: QOM cast cleanupAndreas Färber1-11/+16
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29grlib_irqmp: QOM cast cleanupAndreas Färber1-23/+10
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29exynos4210_gic: QOM cast cleanup for exynos4210.irq_gateAndreas Färber1-9/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29exynos4210_gic: QOM cast cleanup for exynos4210.gicAndreas Färber1-8/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29exynos4210_combiner: QOM cast cleanupAndreas Färber1-9/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29etraxfs_pic: QOM cast cleanupAndreas Färber1-8/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29arm_gic: QOM cast cleanupAndreas Färber3-4/+8
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29imx_avic: QOM cast cleanupAndreas Färber1-10/+17
Introduce type constant, use QOM casts and prepare SysBus initfn for QOM realize by resolving SysBusDevice vs. DeviceState "dev" name conflict. Acked-by: Peter Chubb <peter.chubb@nicta.com.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29xics: rename types to be sane and follow coding styleAnthony Liguori1-112/+233
Basically, in HW the layout of the interrupt network is: - One ICP per processor thread (the "presenter"). This contains the registers to fetch a pending interrupt (ack), EOI, and control the processor priority. - One ICS per logical source of interrupts (ie, one per PCI host bridge, and a few others here or there). This contains the per-interrupt source configuration (target processor(s), priority, mask) and the per-interrupt internal state. Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit oddball what pHyp does here, arguably there are two but we can ignore that distinction). There is no register level access. A pair of firmware (RTAS) calls is used to configure each virtual interrupt. So our model here is somewhat the same. We have one ICS in the emulated XICS which arguably *is* the emulated XICS, there's no point making it a separate "device", that would just be gross, and each VCPU has an associated ICP. Yet we call the "XICS" struct icp_state and then the ICPs 'struct icp_server_state'. It's particularly confusing when all of the functions have xics_prefixes yet take *icp arguments. Rename: struct icp_state -> XICSState struct icp_server_state -> ICPState struct ics_state -> ICSState struct ics_irq_state -> ICSIRQState Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com [aik: added ics_resend() on post_load] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-23ioapic: Use QOM realize for ioapicHu Tao1-7/+5
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> [AF: Tweaked error message] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-11pseries: move interrupt controllers to hw/intc/Alexey Kardashevskiy2-0/+588
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-09intc/openpic: Build openpic only onceAndreas Färber2-2/+2
Since current_cpu is CPUState it no longer depends on CPUPPCState. Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h because hw/ppc/ppc.h is too heavily using CPUPPCState and PowerPCCPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09intc/arm_gic: Build arm_gic only onceAndreas Färber2-1/+2
Since current_cpu is CPUState it no longer needs CPUArchState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-3/+2
Move next_cpu from CPU_COMMON to CPUState. Move first_cpu variable to qom/cpu.h. gdbstub needs to use CPUState::env_ptr for now. cpu_copy() no longer needs to save and restore cpu_next. Acked-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Rebased, simplified cpu_copy()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Replace cpu_single_env with CPUState current_cpuAndreas Färber3-10/+11
Move it to qom/cpu.h. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04hw/i*: pass owner to memory_region_init* functionsPaolo Bonzini19-33/+45
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini21-35/+35
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-01intc/openpic_kvm: Fix QOM and build issuesAndreas Färber1-21/+33
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01intc/openpic: Convert to QOM realizeAndreas Färber1-15/+19
Split qdev initfn into instance_init and realize functions. Change one occurrence of "klass" while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01intc/openpic: QOM'ifyAndreas Färber1-6/+11
Introduce type constant and cast macro. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01kvm/openpic: in-kernel mpic supportScott Wood2-0/+253
Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build, fix ppcemb] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01openpic: factor out some common defines into openpic.hScott Wood1-22/+18
...for use by the KVM in-kernel irqchip stub. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-06-18intc/xilinx_intc: Dont lower IRQ when HIE clearedPeter Crosthwaite1-5/+0
This is a little strange. It is lowering the parent IRQ pin on input when HIE is cleared. There is no such behaviour in the real hardware. ISR changes based on interrupt pin state are already guarded on HIE being set. So we can just delete this if in its entirety. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18intc/xilinx_intc: Inhibit write to ISR when HIEPeter Crosthwaite1-0/+5
When the Hardware Interrupt Enable (HIE) bit is set, software cannot change ISR. Add write guard accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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