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2014-04-03PPC: openpic_kvm: Filter memory events properlyAlexander Graf1-0/+10
Commit 6f1834a2b exposed a bug in openpic_kvm where we don't filter for memory events that only happen to the region we want to know events about. Add proper filtering, fixing the e500plat target with KVM. Signed-off-by: Alexander Graf <agraf@suse.de> Message-id: 1396431718-14908-1-git-send-email-agraf@suse.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-01trace: add workaround for SystemTap PR13296Frank Ch. Eigler1-1/+6
SystemTap sdt.h sometimes results in compiled probes without sufficient information to extract arguments. This can be solved in a slightly hacky way by encouraging the compiler to place arguments into registers. This patch fixes the apic_reset_irq_delivered() trace event on Fedora 20 with gcc-4.8.2-7.fc20 and systemtap-sdt-devel-2.4-2.fc20 on x86_64. Signed-off-by: Frank Ch. Eigler <fche@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-03-27Merge remote-tracking branch 'remotes/afaerber/tags/ppc-for-2.0' into stagingPeter Maydell1-1/+1
PowerPC queue for 2.0 * OpenPIC fix * MSR fixes for POWER7 upwards * TCG instruction set support fix for POWER8 # gpg: Signature made Thu 27 Mar 2014 16:12:12 GMT using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" * remotes/afaerber/tags/ppc-for-2.0: target-ppc: MSR_POW not supported on POWER7/7+/8 target-ppc: POWER7+ supports the MSR_VSX bit target-ppc: POWER8 supports isel target-ppc: POWER8 supports the MSR_LE bit intc/openpic_kvm: Fix MemListener delete region callback function Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-27hw/intc/xilinx_intc: Avoid shifting left into sign bitPeter Maydell1-1/+2
Avoid undefined behaviour shifting left into the sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-27hw/intc/slavio_intctl: Avoid shifting left into sign bitPeter Maydell1-1/+1
Add 'U' suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-27hw/intc/openpic: Avoid shifting left into sign bitPeter Maydell1-7/+7
Add U suffix to avoid undefined behaviour. This is only strictly necessary for the 1 << 31 cases; for consistency we extend it to other constants in the same group. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-27hw/intc/apic.c: Use uint32_t for mask word in foreach_apicPeter Maydell1-3/+3
Use unsigned arithmetic for operations on the mask word in the foreach_apic() macro, to avoid relying on undefined behaviour when shifting into the sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-27intc/openpic_kvm: Fix MemListener delete region callback functionPrasad Joshi1-1/+1
Fixes d85937e683f6ff4d68293cb24c780fb1f6820d2c. Signed-off-by: Prasad Joshi <prasadjoshi.linux@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-15misc: Fix typos in commentsStefan Weil1-1/+1
Codespell found and fixed these new typos: * doesnt -> doesn't * funtion -> function * perfomance -> performance * remaing -> remaining A coding style issue (line too long) was fixed manually. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-13xics-kvm: Fix reset functionAlexey Kardashevskiy1-1/+10
Currently interrupt priorities are set to 0 (highest) at the very beginning of the guest execution which is not correct and makes the guest produce random interrupt error messages such as: "Interrupt 0x1001 (real) is invalid, disabling it". This also prevents interrupt states from correct migration. This initializes priority to 0xFF as the emulated XICS does. Suggested-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-09qemu: x86: ignore ioapic polarityGabriel L. Somlo1-3/+0
Both QEMU and KVM have already accumulated a significant number of optimizations based on the hard-coded assumption that ioapic polarity will always use the ActiveHigh convention, where the logical and physical states of level-triggered irq lines always match (i.e., active(asserted) == high == 1, inactive == low == 0). QEMU guests are expected to follow directions given via ACPI and configure the ioapic with polarity 0 (ActiveHigh). However, even when misbehaving guests (e.g. OS X <= 10.9) set the ioapic polarity to 1 (ActiveLow), QEMU will still use the ActiveHigh signaling convention when interfacing with the emulated ioapic. This patch modifies the emulated ioapic to completely ignore polarity as set by the guest OS, enabling misbehaving guests to work alongside those which comply with the ActiveHigh polarity specified by QEMU's ACPI tables. Signed-off-by: Gabriel L. Somlo <somlo@cmu.edu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-05target-ppc: spapr: e500: fix to use cpu_dt_idAlexey Kardashevskiy3-8/+19
This makes use of @cpu_dt_id and related API in: 1. emulated XICS hypercall handlers as they receive fixed CPU indexes; 2. XICS-KVM to enable in-kernel XICS on right CPU; 3. device-tree renderer. This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor can accept command-line CPU indexes again. This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment KVM CPU id and device tree ID are calculated using the same algorithm. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-04Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140227' ↵Peter Maydell2-0/+323
into staging Several features, fixes and cleanups for kvm/s390: - sclp event facility: cleanup structure. This allows to use realize/unrealize as well as migration support via vmsd - reboot: Two fixes that make reboot much more reliable - ipl: make elf loading more robust - flic interrupt controller: This allows to migrate floating interrupts, as well as clear them on reset etc. - enable async_pf feature of KVM on s390 - several sclp fixes and cleanups - several sigp fixes and cleanups * remotes/borntraeger/tags/kvm-s390-20140227: (22 commits) s390x/ipl: Fix crash of ELF images with arbitrary entry points s390x/kvm: Rework priv instruction handlers s390x/kvm: Add missing SIGP CPU RESET order s390x/kvm: Rework SIGP INITIAL CPU RESET handler s390x/cpu: Use ioctl to reset state in the kernel s390-ccw.img: new binary rom to match latest fixes s390-ccw.img: Fix sporadic errors with ccw boot image - initialize css s390-ccw.img: Fix sporadic reboot hangs: Initialize next_idx s390x/event-facility: exploit realize/unrealize s390x/event-facility: add support for live migration s390x/event-facility: code restructure s390x/event-facility: some renaming s390x/sclp: Fixed setting of condition code register s390x/sclp: Add missing checks to SCLP handler s390x/sclp: Fixed the size of sccb and code parameter s390x/eventfacility: mask out commands s390x/virtio-hcall: Specification exception for illegal subcodes s390x/virtio-hcall: Add range check for hypervisor call s390x/kvm: Fixed bad SIGP SET-ARCHITECTURE handler s390x/async_pf: Check for apf extension and enable pfault ... Conflicts: linux-headers/linux/kvm.h Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-27s390x/async_pf: Check for apf extension and enable pfaultDominik Dingel1-0/+36
S390 can also use async page faults, to enhance guest scheduling. In case of live migration we want to disable the feature and let all pending request finish. Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-02-27s390x/kvm: implement floating-interrupt controller deviceJens Freimann2-0/+287
This patch implements a floating-interrupt controller device (flic) which interacts with the s390 flic kvm_device. Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2014-02-26hw: arm_gic_kvm: Add KVM VGIC save/restore logicChristoffer Dall1-2/+422
Save and restore the ARM KVM VGIC state from the kernel. We rely on QEMU to marshal the GICState data structure and therefore simply synchronize the kernel state with the QEMU emulated state in both directions. We take some care on the restore path to check the VGIC has been configured with enough IRQs and CPU interfaces that we can properly restore the state, and for separate set/clear registers we first fully clear the registers and then set the required bits. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687921-26921-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26arm: vgic device control api supportChristoffer Dall1-2/+20
Support creating the ARM vgic device through the device control API and setting the base address for the distributor and cpu interfaces in KVM VMs using this API. Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be created prior to creating the VCPUs, we first test if we can use the device control API in kvm_arch_irqchip_create (using the test flag from the device control API). If we cannot, it means we have to fall back to KVM_CREATE_IRQCHIP and use the older ioctl at this point in time. If however, we can use the device control API, we don't do anything and wait until the arm_gic_kvm driver initializes and let that use the device control API. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1392687720-26806-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26hw/intc/arm_gic: Fix GIC_SET_LEVELChristoffer Dall1-1/+1
The GIC_SET_LEVEL macro unfortunately overwrote the entire level bitmask instead of just or'ing on the necessary bits, causing active level PPIs on a core to clear PPIs on other cores. Cc: qemu-stable@nongnu.org Reported-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1393031030-8692-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-26hw/intc/exynos4210_combiner: Don't overrun output_irq array in initPeter Maydell1-1/+1
The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs; use the correct constant in the loop initializing our output sysbus IRQs so that we don't overrun the output_irq[] array. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392659611-8439-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Andreas Färber <afaerber@suse.de> Cc: qemu-stable@nongnu.org
2014-02-21Merge remote-tracking branch ↵Peter Maydell1-1/+1
'remotes/pmaydell/tags/pull-target-arm-20140220' into staging target-arm queue: * Fix a bug causing an assertion in the NVIC on ARMv7M models * More A64 Neon instructions * Refactor cpreg API to separate out access check functions, as groundwork for AArch64 system mode * Fix bug in linux-user A64 store-exclusive of XZR # gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits) linux-user: AArch64: Fix exclusive store of the zero register target-arm: A64: Implement unprivileged load/store target-arm: A64: Implement narrowing three-reg-diff operations target-arm: A64: Implement the wide 3-reg-different operations target-arm: A64: Add most remaining three-reg-diff widening ops target-arm: A64: Add opcode comments to disas_simd_three_reg_diff target-arm: A64: Implement store-exclusive for system mode target-arm: Fix incorrect type for value argument to write_raw_cp_reg target-arm: Remove failure status return from read/write_raw_cp_reg target-arm: Remove unnecessary code now read/write fns can't fail target-arm: Drop success/fail return from cpreg read and write functions target-arm: Convert miscellaneous reginfo structs to accessfn target-arm: Convert generic timer reginfo to accessfn target-arm: Convert performance monitor reginfo to accessfn target-arm: Split cpreg access checks out from read/write functions target-arm: Stop underdecoding ARM946 PRBS registers target-arm: Log bad system register accesses with LOG_UNIMP target-arm: Remove unused ARMCPUState sr substruct target-arm: Restrict check_ap() use of S and R bits to v6 and earlier target-arm: Define names for SCTLR bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20hw/intc/arm_gic: Fix NVIC assertion failurePeter Maydell1-1/+1
Commit 40d225009ef accidentally changed the behaviour of gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs, so this meant we hit an assertion: gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed. Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2014-02-14qdev: Remove hex8/32/64 property typesPaolo Bonzini1-3/+3
Replace them with uint8/32/64. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-11exec: Make cpu_physical_memory_write_rom input an ASEdgar E. Iglesias1-1/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-08arm_gic: Add GICC_APRn state to the GICStateChristoffer Dall2-2/+8
The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm_gic: Support setting/getting binary point regChristoffer Dall2-5/+13
Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm_gic: Keep track of SGI sourcesChristoffer Dall2-14/+89
Right now the arm gic emulation doesn't keep track of the source of an SGI (which apparently Linux guests don't use, or they're fine with assuming CPU 0 always). Add the necessary matrix on the GICState structure and maintain the data when setting and clearing the pending state of an IRQ and make the state visible to the guest. Note that we always choose to present the source as the lowest-numbered CPU in case multiple cores have signalled the same SGI number to a core on the system. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08arm_gic: Fix GIC pending behaviorChristoffer Dall2-18/+62
The existing implementation of the pending behavior in gic_set_irq, gic_complete_irq, and the distributor pending set/clear registers does not follow the semantics of the GICv2.0 specs, but may implement the 11MPCore support. Therefore, maintain the existing semantics for 11MPCore and v7M NVIC and change the behavior to be in accordance with the GICv2.0 specs for "generic implementations" (s->revision == 1 || s->revision == 2). Generic implementations distinguish between setting a level-triggered interrupt pending through writes to the GICD_ISPENDR and when hardware raises the interrupt line. Writing to the GICD_ICPENDR will not cause the interrupt to become non-pending if the line is still active, and conversely, if the line is deactivated but the interrupt is marked as pending through a write to GICD_ISPENDR, the interrupt remains pending. Handle this situation in the GIC_TEST_PENDING (which now becomes a static inline named gic_test_pending) and let the 'pending' field correspond only to the latched state of the D-flip flop in the GICv2.0 specs Figure 4-10. The following changes are added: gic_test_pending: Make this a static inline and split out the 11MPCore from the generic behavior. For the generic behavior, consider interrupts pending if: ((s->irq_state[irq].pending & (cm) != 0) || (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm)) gic_set_irq: Split out the 11MPCore from the generic behavior. For the generic behavior, always GIC_SET_LEVEL() on positive level, but only GIC_SET_PENDING for edge-triggered interrupts and always simply GIC_CLEAR_LEVEL() on negative level. gic_complete_irq: Only resample the line for line-triggered interrupts on an 11MPCore. Generic implementations will sample the line directly in gic_test_pending(). Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writesChristoffer Dall1-1/+5
Fix two bugs that would allow changing the state of SGIs through the ICPENDR and ISPENDRs. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31arm_gic: Introduce define for GIC_NR_SGISChristoffer Dall1-6/+11
Instead of hardcoding 16 various places in the code, use a define to make it more clear what is going on. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-09Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into ↵Anthony Liguori12-74/+104
staging QOM infrastructure fixes and device conversions * QOM interface fixes and unit test * Device no_user sanitization and documentation * Device error reporting improvement * Conversion of APIC, ICC, IOAPIC to QOM realization model # gpg: Signature made Tue 24 Dec 2013 09:04:05 AM PST using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F * afaerber/tags/qom-devices-for-anthony: (24 commits) qdev-monitor: Improve error message for -device nonexistant ioapic: QOM'ify ioapic ioapic: Cleanup for QOM'ification icc_bus: QOM'ify ICC apic: QOM'ify APIC apic: Cleanup for QOM'ification qdev: Drop misleading qbus_free() function qom: Detect bad reentrance during object_class_foreach() tests: Test QOM interface casting qom: Do not register interface "types" in the type table and fix names qom: Split out object and class caches qdev: Document that pointer properties kill device_add hw: cannot_instantiate_with_device_add_yet due to pointer props qdev-monitor: Avoid device_add crashing on non-device driver name qdev: Do not let the user try to device_add when it cannot work isa: Clean up use of cannot_instantiate_with_device_add_yet vt82c686: Clean up use of cannot_instantiate_with_device_add_yet piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet ich9: Document why cannot_instantiate_with_device_add_yet pci-host: Consistently set cannot_instantiate_with_device_add_yet ...
2014-01-08hw: arm_gic: Introduce gic_set_priority functionChristoffer Dall2-5/+11
To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGERChristoffer Dall3-11/+11
TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-24ioapic: QOM'ify ioapicxiaoqiang zhao2-6/+16
Convert 'init' function to QOM's 'realize' for ioapic and kvm-ioapic. Change variable 'ioapic_no' from static to global. Then we can drop the 'instance_no' function argument. Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-24ioapic: Cleanup for QOM'ificationxiaoqiang zhao2-3/+5
Some cleanups: * ioapic_common.c: Rename 'register_types' to 'ioapic_common_register_types' * Replace inline 'DEVICE(s)' with local 'DeviceState *dev' variable Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-24icc_bus: QOM'ify ICCxiaoqiang zhao1-6/+7
For consistency, QOM'ify APIC's parent bus. Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-24apic: QOM'ify APICxiaoqiang zhao2-3/+5
Convert 'init' function to QOM's 'realize' for apic, kvm/apic and xen/xen_apic. Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-24apic: Cleanup for QOM'ificationxiaoqiang zhao2-51/+51
Do some cleanup, including: 1. Remove DO_UPCAST() for APICCommonState 2. Change DeviceState pointers from 'd' to 'dev', better to understand 3. Rename 'register_types' to specifically 'apic_common_register_types' Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-24hw: cannot_instantiate_with_device_add_yet due to pointer propsMarkus Armbruster3-0/+10
Pointer properties can be set only by code, not by device_add. A device with a pointer property can work with device_add only when the property may remain null. This is the case for property "interrupt_vector" of device "etraxfs,pic". Add a comment there. Set cannot_instantiate_with_device_add_yet for the other devices with pointer properties, with a comment explaining why. Juha Riihimäki and Peter Maydell deserve my thanks for making "pointer property must not remain null" blatantly obvious in the OMAP devices. Only device "smbus-eeprom" is actually changed. The others are all sysbus devices, which get cannot_instantiate_with_device_add_yet set in their abstract base's class init function. Setting it again in their class init function is technically redundant, but serves as insurance for when sysbus devices become available with device_add, and as documentation. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for ETRAX) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23isa: Clean up use of cannot_instantiate_with_device_add_yetMarkus Armbruster1-1/+7
Drop it when there's no obvious reason why device_add could not work. Else keep and document why. * isa-fdc: drop * i8042: drop, even though its I/O base is hardcoded (because you could conceivably still add one to a board that has none), and even though PC board code wires up the A20 line (because that wiring is optional) * port92: keep because it needs additional wiring by port92_init() * mc146818rtc: keep because it needs to be wired up by rtc_init() * m48t59_isa: keep because needs to be wired up by m48t59_init_isa() * isa-pit, kvm-pit: keep (in their abstract base pic-common) because the PIT needs additional wiring by board code, depending on HPET presence * pcspk: keep because of pointer property pit, and because realize sets global pcspk_state * vmmouse: keep because of pointer property ps2_mouse * vmport: keep because realize sets global port_state * isa-i8259, kvm-i8259: keep (in their abstract base pic-common), because the PICs' IRQ input lines are set up by board code, and the wiring of the slave to the master is hard-coded in device model code Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23apic: Document why cannot_instantiate_with_device_add_yetMarkus Armbruster1-1/+5
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23sysbus: Set cannot_instantiate_with_device_add_yetMarkus Armbruster5-5/+0
device_add plugs devices into suitable bus. For "real" buses, that actually connects the device. For sysbus, the connections need to be made separately, and device_add can't do that. The device would be left unconnected, and could not possibly work. Quite a few, but not all sysbus devices already set cannot_instantiate_with_device_add_yet in their class init function. Set it in their abstract base's class init function sysbus_device_class_init(), and remove the now redundant assignments from device class init functions. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23qdev: Replace no_user by cannot_instantiate_with_device_add_yetMarkus Armbruster7-7/+7
In an ideal world, machines can be built by wiring devices together with configuration, not code. Unfortunately, that's not the world we live in right now. We still have quite a few devices that need to be wired up by code. If you try to device_add such a device, it'll fail in sometimes mysterious ways. If you're lucky, you get an unmysterious immediate crash. To protect users from such badness, DeviceClass member no_user used to make device models unavailable with -device / device_add, but that regressed in commit 18b6dad. The device model is still omitted from help, but is available anyway. Attempts to fix the regression have been rejected with the argument that the purpose of no_user isn't clear, and it's prone to misuse. This commit clarifies no_user's purpose. Anthony suggested to rename it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which I shorten somewhat to keep checkpatch happy. While there, make it bool. Every use of cannot_instantiate_with_device_add_yet gets a FIXME comment asking for rationale. The next few commits will clean them all up, either by providing a rationale, or by getting rid of the use. With that done, the regression fix is hopefully acceptable. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-20spapr-rtas: replace return code constants with macrosAlexey Kardashevskiy1-12/+12
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-17hw/intc: add allwinner A10 interrupt controllerliguang2-0/+201
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-05realview_gic: Prepare for QOM embeddingAndreas Färber1-14/+1
Move state struct, type constant and cast macro to a new header. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05realview_gic: Convert to QOM realizeAndreas Färber1-16/+35
Embed GICState and replace SysBus initfn with realizefn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm_gic: Extract headers hw/intc/arm_gic{,_common}.hAndreas Färber2-87/+11
Rename NCPU to GIC_NCPU and move GICState away from gic_internal.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-10-25xics-kvm: enable irqfd for MSIAlexey Kardashevskiy1-0/+6
This enables IRQFD support for sPAPR. The feature decreases the latency of interrupt handling. To enable IRQFD for MSI, this sets kvm_gsi_direct_mapping to true which enables direct MSI mapping. To enable IRQFD for LSI (level triggered INTx interrupts), a PCI host bus callback is required. The patch for that is coming next. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: Implement H_XIRR_XBenjamin Herrenschmidt1-0/+14
This implements H_XIRR_X hypercall in addition to H_XIRR as it is mandatory for PAPR+ and there is no way for the guest to detect whether it is supported or not so just add it. As the Partition Adjunct Option is not supported at the moment, the CPPR parameter of the hypercall is ignored. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25xics: Implement H_IPOLLBenjamin Herrenschmidt1-0/+13
This adds support for the H_IPOLL hypercall which the guest uses to poll for a pending interrupt. This hypercall is mandatory for PAPR+ and there is no way for the guest to detect whether it is supported or not so just add it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
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