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AgeCommit message (Expand)AuthorFilesLines
2022-12-15hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase resetPeter Maydell1-5/+9
2022-12-15hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase resetPeter Maydell1-5/+9
2022-12-15hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase resetPeter Maydell1-3/+4
2022-12-15hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase resetPeter Maydell1-5/+9
2022-12-15hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase resetPeter Maydell1-3/+4
2022-12-15hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase resetPeter Maydell1-5/+9
2022-12-15hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase resetPeter Maydell1-3/+4
2022-12-15hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisementLuke Starrett1-2/+2
2022-11-21hw/intc: add implementation of GICD_IIDR to Arm GICAlex Bennée1-1/+11
2022-11-21hw/intc: clean-up access to GIC multi-byte registersAlex Bennée1-6/+10
2022-11-14hw/intc/arm_gicv3: fix prio masking on pmr writeJens Wiklander1-2/+1
2022-11-04hw/intc: Fix LoongArch extioi coreisr accessingXiaojuan Yang1-4/+6
2022-11-04hw/intc: Convert the memops to with_attrs in LoongArch extioiXiaojuan Yang2-16/+18
2022-10-31hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.hBALATON Zoltan2-2/+0
2022-10-17hw/intc: Fix LoongArch ipi device emulationXiaojuan Yang1-1/+0
2022-10-14hw/intc: sifive_plic: change interrupt priority register to WARL fieldJim Shu1-2/+19
2022-10-14hw/intc: sifive_plic: fix hard-coded max priority levelJim Shu1-2/+4
2022-09-22hw/intc/xics: Avoid dynamic stack allocationPhilippe Mathieu-Daudé1-1/+1
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra1-14/+34
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-1/+3
2022-08-31hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR deviceBALATON Zoltan1-20/+6
2022-08-01misc: fix commonly doubled up wordsDaniel P. Berrangé1-1/+1
2022-07-28hw/intc: sifive_plic: Fix multi-socket plic configuraitonAtish Patra1-2/+2
2022-07-19hw/intc/loongarch_pch_pic: Fix bugs for update_irq functionXiaojuan Yang1-5/+5
2022-07-18ppc64: Allocate IRQ lines with qdev_init_gpio_in()Cédric Le Goater2-6/+8
2022-07-18hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held highPeter Maydell1-1/+8
2022-07-06ppc: Define SETFIELD for the ppc targetAlexey Kardashevskiy2-40/+0
2022-07-05hw/intc/loongarch_ipi: Fix mail send and any send functionXiaojuan Yang1-23/+31
2022-07-05hw/intc/loongarch_ipi: Fix ipi device access of 64bitsXiaojuan Yang1-7/+31
2022-07-04hw/intc/loongarch_pch_msi: Fix msi vector convertionMao Bibo1-2/+20
2022-06-28Trivial: 3 char repeat typosDr. David Alan Gilbert1-1/+1
2022-06-20pnv/xive2: Access direct mapped thread contexts from all chipsFrederic Barrat1-4/+14
2022-06-10hw/intc: sifive_plic: Avoid overflowing the addr_config bufferAlistair Francis1-10/+9
2022-06-08Fix 'writeable' typosPeter Maydell5-6/+6
2022-06-06hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)Xiaojuan Yang4-0/+322
2022-06-06hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)Xiaojuan Yang4-0/+82
2022-06-06hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)Xiaojuan Yang4-0/+445
2022-06-06hw/loongarch: Add LoongArch ipi interrupt support(IPI)Xiaojuan Yang4-0/+250
2022-05-26pnv/xive2: Don't overwrite PC registers when writing TCTXT registersFrederic Barrat1-3/+0
2022-05-24hw/intc: Pass correct hartid while updating mtimecmpAtish Patra1-1/+2
2022-05-19hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell1-6/+10
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell2-4/+16
2022-05-19hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell1-54/+128
2022-05-19hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constantPeter Maydell1-3/+13
2022-05-19hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell1-1/+1
2022-05-19hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell1-5/+13
2022-05-05ppc/xive: Update the state of the External interrupt signalFrederic Barrat2-0/+16
2022-05-05ppc/xive: Always recompute the PIPR when pushing an OS contextFrederic Barrat2-10/+17
2022-05-05target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson2-6/+0
2022-05-05target/arm: Split out cpregs.hRichard Henderson2-0/+3
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