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AgeCommit message (Expand)AuthorFilesLines
2018-02-09s390x/tcg: cache the qemu flic in a central functionDavid Hildenbrand1-6/+17
2018-02-09s390x/flic: optimize CPU wakeup for TCGDavid Hildenbrand1-2/+29
2018-02-09s390x/flic: implement qemu_s390_clear_io_flic()David Hildenbrand1-2/+29
2018-02-09s390x/flic: make floating interrupts on TCG actually floatingDavid Hildenbrand1-10/+134
2018-02-09s390x/flic: no need to call s390_io_interrupt() from flicDavid Hildenbrand1-1/+2
2018-02-09s390x/flic: factor out injection of floating interruptsDavid Hildenbrand2-5/+89
2018-02-09s390x/tcg: simplify lookup of flicDavid Hildenbrand1-5/+3
2018-02-09s390x/flic: simplify flic initializationDavid Hildenbrand2-14/+5
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé6-16/+10
2018-01-26xlnx-zynqmp-ipi: Initial version of the Xilinx IPI deviceAlistair Francis2-0/+378
2018-01-26xlnx-pmu-iomod-intc: Add the PMU Interrupt controllerAlistair Francis2-0/+555
2018-01-25Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180125'...Peter Maydell1-4/+21
2018-01-25hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1Luc MICHEL1-3/+13
2018-01-25hw/intc/arm_gic: Fix group priority computation for group 1 IRQsLuc MICHEL1-1/+2
2018-01-25hw/intc/arm_gic: Fix C_RPR value on idle priorityLuc MICHEL1-0/+5
2018-01-25hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and ...Luc MICHEL1-0/+1
2018-01-24sparc/leon3 irqmp: fix IRQ software ackJean-Christophe Dubois1-6/+11
2018-01-22Replace all occurances of __FUNCTION__ with __func__Alistair Francis1-1/+1
2018-01-16hw/intc/armv7m: Support byte and halfword accesses to CFSRPeter Maydell1-16/+22
2018-01-11hw/intc/arm_gic: reserved register addresses are RAZ/WIPeter Maydell1-2/+3
2018-01-11hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell3-5/+29
2018-01-09sun4m: remove include/hw/sparc/sun4m.h and all references to itMark Cave-Ayland1-1/+0
2017-12-22apic: add function to apic that will be used by hvfSergio Andres Gomez Del Real1-0/+12
2017-12-21i8259: move TYPE_INTERRUPT_STATS_PROVIDER upperPeter Xu2-7/+7
2017-12-21kvm-i8259: support "info pic" and "info irq"Peter Xu1-0/+1
2017-12-21i8259: generalize statistics into common codePeter Xu2-36/+42
2017-12-21i8259: use DEBUG_IRQ_COUNT alwaysPeter Xu1-17/+1
2017-12-21i8259: convert DPRINTFs into tracePeter Xu2-15/+18
2017-12-18misc: drop old i386 dependencyPhilippe Mathieu-Daudé1-1/+0
2017-12-15spapr: introduce a spapr_qirq() helperCédric Le Goater1-12/+0
2017-12-15spapr: move the IRQ allocation routines under the machineCédric Le Goater2-118/+0
2017-12-15ppc/xics: assign of the CPU 'intc' pointer under the coreCédric Le Goater1-1/+0
2017-12-15ppc/xics: introduce an icp_create() helperCédric Le Goater1-0/+21
2017-12-15openpic: debug w/ info_report()Michael Davidsaver1-51/+51
2017-12-15ppc/xics: remove useless if conditionCédric Le Goater1-4/+2
2017-12-13nvic: Make systick bankedPeter Maydell1-13/+77
2017-12-13nvic: Make nvic_sysreg_ns_ops work with any MemoryRegionPeter Maydell1-3/+7
2017-12-13hw/intc/arm_gicv3_its: Implement full resetEric Auger1-1/+8
2017-12-13hw/intc/arm_gicv3_its: Implement a minimalist resetEric Auger1-0/+42
2017-12-13hw/intc/arm_gicv3_its: Don't call post_load on resetEric Auger2-6/+0
2017-11-20nvic: Fix ARMv7M MPU_RBAR readsPeter Maydell1-1/+1
2017-11-16Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-16/+6
2017-11-14ioapic/tracing: Remove last DPRINTFsDr. David Alan Gilbert2-16/+6
2017-11-14xics/kvm: synchonize state before 'info pic'Greg Kurz2-0/+30
2017-11-07hw/intc/arm_gicv3_its: Don't abort on table save failureEric Auger1-6/+2
2017-11-07hw/intc/arm_gicv3_its: Fix the VM termination in vm_change_state_handler()Shanker Donthineni1-2/+2
2017-10-21openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)Stafford Horne2-0/+180
2017-10-12nvic: Fix miscalculation of offsets into ITNS arrayPeter Maydell1-2/+2
2017-10-12nvic: Add missing 'break'Peter Maydell1-0/+1
2017-10-06nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bitPeter Maydell1-0/+1
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