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AgeCommit message (Expand)AuthorFilesLines
2017-09-21nvic: Support banked exceptions in acknowledge and completePeter Maydell1-2/+2
2017-09-21nvic: Make SHPR registers bankedPeter Maydell1-1/+1
2017-09-21nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell1-2/+2
2017-09-21nvic: Handle banked exceptions in nvic_recompute_state()Peter Maydell1-0/+1
2017-09-21nvic: Add cached vectpending_prio statePeter Maydell1-1/+1
2017-08-01trace-events: fix code style: print 0x before hex numbersVladimir Sementsov-Ogievskiy1-78/+78
2017-08-01trace-events: fix code style: %# -> 0x%Vladimir Sementsov-Ogievskiy1-10/+10
2017-07-31docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé1-1/+1
2017-07-14s390x/flic: introduce inject_airq callbackYi Min Zhao1-0/+4
2017-02-28armv7m: Rewrite NVIC to not use any GIC codeMichael Davidsaver1-0/+15
2017-01-31trace: clean up trace-events filesStefan Hajnoczi1-1/+0
2017-01-20Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-0/+7
2017-01-20hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()Peter Maydell1-0/+2
2017-01-20hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IARPeter Maydell1-0/+2
2017-01-20hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registersPeter Maydell1-0/+3
2017-01-20hw/intc/arm_gicv3: Implement ICV_ registers which are just accessorsPeter Maydell1-0/+10
2017-01-20hw/intc/arm_gicv3: Add accessors for ICH_ system registersPeter Maydell1-0/+16
2017-01-16x86: ioapic: add traces for ioapicPeter Xu1-0/+7
2016-10-17hw/intc/arm_gicv3: Fix ICC register tracepointsPeter Maydell1-7/+7
2016-10-14ppc/xics: Split ICS into ics-base and ics classBenjamin Herrenschmidt1-5/+5
2016-10-14ppc/xics: Make the ICSState a listBenjamin Herrenschmidt1-2/+3
2016-08-12trace-events: fix first line comment in trace-eventsLaurent Vivier1-1/+1
2016-06-20trace: split out trace events for hw/intc/ directoryDaniel P. Berrange1-0/+123