riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2023-06-05	bulk: Remove pointless QOM casts	Philippe Mathieu-Daudé	1	-3/+3
	Mechanical change running Coccinelle spatch with content generated from the qom-cast-macro-clean-cocci-gen.py added in the previous commit. Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230601093452.38972-3-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-15	hw/loongarch/virt: Set max 256 cpus support on loongarch virt machine	Song Gao	1	-2/+2
	Add separate macro EXTIOI_CPUS for extioi interrupt controller, extioi only supports 4 cpu. And set macro LOONGARCH_MAX_CPUS as 256 so that loongarch virt machine supports more cpus. Interrupts from external devices can only be routed cpu 0-3 because of extioi limits, cpu internal interrupt such as timer/ipi can be triggered on all cpus. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230512100421.1867848-3-gaosong@loongson.cn>
2022-11-04	hw/intc: Fix LoongArch extioi coreisr accessing	Xiaojuan Yang	1	-4/+6
	1. When cpu read or write extioi COREISR reg, it should access the reg belonged to itself, so the cpu index of 's->coreisr' is current cpu number. Using MemTxAttrs' requester_id to get the cpu index. 2. it need not to mask 0x1f when calculate the coreisr array index. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-11-04	hw/intc: Convert the memops to with_attrs in LoongArch extioi	Xiaojuan Yang	1	-14/+17
	Converting the MemoryRegionOps read/write handlers to with_attrs in LoongArch extioi emulation. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-06-06	hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)	Xiaojuan Yang	1	-0/+312
	This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-35-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>