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path: root/hw/intc/arm_gicv3_dist.c
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2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé1-4/+4
2022-12-15hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisementLuke Starrett1-2/+2
2022-06-08Fix 'writeable' typosPeter Maydell1-1/+1
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell1-3/+4
2022-04-22hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell1-1/+1
2022-03-07hw/intc/arm_gicv3: Fix missing spaces in error log messagesPeter Maydell1-2/+2
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela1-1/+4
2021-09-01hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleansPhilippe Mathieu-Daudé1-95/+106
2021-09-01hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffixPhilippe Mathieu-Daudé1-6/+6
2019-06-17hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1Peter Maydell1-1/+7
2019-06-17hw/intc/arm_gicv3: Fix decoding of ID register rangePeter Maydell1-2/+2
2018-06-22hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYRAmol Surati1-1/+2
2018-01-11hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell1-0/+13
2016-06-20hw/intc/arm_gicv3: Fix compilation with simple trace backendPeter Maydell1-0/+1
2016-06-17hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell1-0/+21
2016-06-17hw/intc/arm_gicv3: Implement GICv3 distributor registersShlomo Pongratz1-0/+858
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