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AgeCommit message (Expand)AuthorFilesLines
2013-07-04hw/d*: pass owner to memory_region_init* functionsPaolo Bonzini7-7/+9
2013-07-04piolist: add owner argument to initialization functions and pass devicesPaolo Bonzini1-1/+1
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini11-14/+14
2013-07-04i82374: replace register_ioport*Jan Kiszka1-5/+13
2013-06-20dma: eliminate DMAContextPaolo Bonzini1-4/+4
2013-06-15Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpuBlue Swirl1-8/+5
2013-06-10xilinx_axidma: Do not set DMA .notify to NULL after notifyWendy Liang1-1/+2
2013-06-07isa: Use realizefn for ISADeviceAndreas Färber1-8/+5
2013-05-20Rename hexdump to avoid FreeBSD libutil conflictEd Maste1-2/+2
2013-04-29i82374: QOM'ifyAndreas Färber1-3/+7
2013-04-20qdev: Drop taddr propertiesPeter Maydell1-1/+0
2013-04-19Remove unneeded type castsStefan Weil2-3/+3
2013-04-16stream: Remove app argument hackPeter Crosthwaite1-29/+70
2013-04-16xilinx_axienet/dma: Implement rx path flow controlPeter Crosthwaite1-8/+41
2013-04-16stream: Add flow control APIPeter Crosthwaite1-1/+2
2013-04-16xilinx_axidma: Fix rx/tx halted bit.Peter Crosthwaite1-2/+2
2013-04-16xilinx_axidma: Create Proxy object for streamPeter Crosthwaite1-5/+58
2013-04-16xilinx_axidma: converted init->realizePeter Crosthwaite1-13/+13
2013-04-16xilinx_axidma: Register reset properlyPeter Crosthwaite1-1/+11
2013-04-16xilinx_axidma: Defined and use type cast macroPeter Crosthwaite1-4/+9
2013-04-16xilinx_axidma: typedef XilinxAXIDMA structPeter Crosthwaite1-7/+9
2013-04-08hw: move DMA controllers to hw/dma/, configure with default-configs/Paolo Bonzini7-0/+4530
2013-04-08hw: move target-independent files to subdirectoriesPaolo Bonzini8-0/+4306
2013-04-08hw: make subdirectories for devicesPaolo Bonzini1-0/+0
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