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AgeCommit message (Expand)AuthorFilesLines
2023-04-24hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEVJonathan Cameron1-2/+2
2023-03-07hw/pxb-cxl: Support passthrough HDM Decoders unless overriddenJonathan Cameron1-12/+19
2023-03-07hw/mem/cxl_type3: Add CXL RAS Error Injection Support.Jonathan Cameron1-1/+3
2023-03-07hw/cxl: Fix endian issues in CXL RAS capability defaults / masksJonathan Cameron1-9/+9
2023-03-02hw/cxl/mailbox: Use new UUID network order define for cel_uuidIra Weiny2-8/+7
2023-03-02hw/cxl: Add CXL_CAPACITY_MULTIPLIER definitionGregory Price1-6/+9
2023-01-17hw/cxl/cxl-host: Fix an error message typoHoa Nguyen1-1/+1
2023-01-16hw/cxl/cxl-cdat.c: spelling: missmatchMichael Tokarev1-1/+1
2022-11-07hw/cxl/cdat: CXL CDAT Data Object Exchange implementationHuai-Cheng Kuo2-0/+225
2022-08-17hw/cxl: Correctly handle variable sized mailbox input payloads.Jonathan Cameron1-1/+1
2022-08-17hw/cxl: Fix Get LSA input payload size which should be 8 bytes.Jonathan Cameron1-1/+1
2022-08-17hw/cxl: Add stub write function for RO MemoryRegionOps entries.Jonathan Cameron1-3/+9
2022-08-17hw/cxl: Fix wrong query of target portsJonathan Cameron1-7/+5
2022-08-17hw/cxl: Fix memory leak in error pathsJonathan Cameron1-2/+3
2022-06-16pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron1-2/+41
2022-06-09hw/cxl: Fix missing write mask for HDM decoder target list registersJonathan Cameron1-2/+11
2022-06-09pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.Jonathan Cameron2-0/+21
2022-06-09hw/cxl: Push linking of CXL targets into i386/pc rather than in machine.cJonathan Cameron2-6/+4
2022-06-09hw/cxl: Make the CXL fixed memory window setup a machine parameter.Jonathan Cameron2-9/+69
2022-05-13hw/cxl/component Add a dumb HDM decoder handlerBen Widawsky1-0/+31
2022-05-13cxl/cxl-host: Add memops for CFMWS region.Jonathan Cameron2-0/+130
2022-05-13hw/cxl/host: Add support for CXL Fixed Memory Windows.Jonathan Cameron3-0/+114
2022-05-13hw/cxl/component: Add utils for interleave parameter encoding/decodingJonathan Cameron1-0/+34
2022-05-13hw/cxl/device: Implement get/set Label Storage Area (LSA)Ben Widawsky1-0/+60
2022-05-13hw/cxl/device: Plumb real Label Storage Area (LSA) sizingBen Widawsky1-0/+3
2022-05-13hw/cxl/device: Add some trivial commandsBen Widawsky1-0/+69
2022-05-13hw/cxl/device: Add a memory device (8.2.8.5)Ben Widawsky2-0/+64
2022-05-13hw/cxl/device: Add log commands (8.2.9.4) + CELBen Widawsky1-0/+69
2022-05-13hw/cxl/device: Timestamp implementation (8.2.9.3)Ben Widawsky1-0/+42
2022-05-13hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)Ben Widawsky1-1/+26
2022-05-13hw/cxl/device: Add memory device utilitiesBen Widawsky1-1/+37
2022-05-13hw/cxl/device: Implement basic mailbox (8.2.8.4)Ben Widawsky3-1/+286
2022-05-13hw/cxl/device: Implement the CAP array (8.2.8.1-2)Ben Widawsky2-0/+110
2022-05-13hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)Ben Widawsky3-0/+320