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path: root/hw/cxl/cxl-component-utils.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-15hw/cxl: spelling fixes: limitaions, potentialy, intializedMichael Tokarev1-2/+2
2023-11-07hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.Jonathan Cameron1-1/+0
2023-11-07hw/cxl: Line length reductionsJonathan Cameron1-6/+8
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron1-20/+29
2023-11-07hw/cxl: Use switch statements for read and write of cachemem registersJonathan Cameron1-23/+43
2023-10-04hw/cxl: Support 4 HDM decoders at all levels of topologyJonathan Cameron1-2/+5
2023-10-04hw/cxl: Fix and use same calculation for HDM decoder block size everywhereJonathan Cameron1-8/+11
2023-10-04hw/cxl: Add utility functions decoder interleave ways and target count.Jonathan Cameron1-6/+54
2023-10-04hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .cJonathan Cameron1-0/+18
2023-05-19hw/cxl: Fix incorrect reset of commit and associated clearing of committed.Jonathan Cameron1-1/+5
2023-05-19hw/cxl: Fix endian handling for decoder commit.Jonathan Cameron1-4/+4
2023-05-19hw/cxl: drop pointless memory_region_transaction_guardsJonathan Cameron1-2/+0
2023-03-07hw/mem/cxl_type3: Add CXL RAS Error Injection Support.Jonathan Cameron1-1/+3
2023-03-07hw/cxl: Fix endian issues in CXL RAS capability defaults / masksJonathan Cameron1-9/+9
2022-06-09hw/cxl: Fix missing write mask for HDM decoder target list registersJonathan Cameron1-2/+11
2022-05-13hw/cxl/component Add a dumb HDM decoder handlerBen Widawsky1-0/+31
2022-05-13hw/cxl/component: Add utils for interleave parameter encoding/decodingJonathan Cameron1-0/+34
2022-05-13hw/cxl/device: Add a memory device (8.2.8.5)Ben Widawsky1-0/+18
2022-05-13hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)Ben Widawsky1-0/+313