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2013-04-08hw: move interrupt controllers to hw/intc/, configure with default-configs/Paolo Bonzini1-553/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move headers to include/Paolo Bonzini1-1/+1
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-05arm_gic: Fix sizes of state fields in preparation for vmstate supportPeter Maydell1-2/+2
In preparation for switching to vmstate for migration support, fix the sizes of various GIC state fields. In particular, we replace all the bitfields (which VMState can't deal with) with straightforward uint8_t values which we do bit operations on. (The bitfields made more sense when NCPU was set differently in different situations, but we now always model at the architectural limit of 8.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1363975375-3166-3-git-send-email-peter.maydell@linaro.org
2013-03-10Merge remote-tracking branch 'bonzini/hw-dirs' into stagingAnthony Liguori1-3/+3
* bonzini/hw-dirs: sh: move files referencing CPU to hw/sh4/ ppc: move more files to hw/ppc ppc: move files referencing CPU to hw/ppc/ m68k: move files referencing CPU to hw/m68k/ i386: move files referencing CPU to hw/i386/ arm: move files referencing CPU to hw/arm/ hw: move boards and other isolated files to hw/ARCH ppc: express FDT dependency of pSeries and e500 boards via default-configs/ build: always link device_tree.o into emulators if libfdt available hw: include hw header files with full paths ppc: do not use ../ in include files vt82c686: vt82c686 is not a PCI host bridge virtio-9p: remove PCI dependencies from hw/9pfs/ virtio-9p: use CONFIG_VIRTFS, not CONFIG_LINUX hw: move device-hotplug.o to toplevel, compile it once hw: move qdev-monitor.o to toplevel directory hw: move fifo.[ch] to libqemuutil hw: move char backends to backends/ Conflicts: backends/baum.c backends/msmouse.c hw/a15mpcore.c hw/arm/Makefile.objs hw/arm/pic_cpu.c hw/dataplane/event-poll.c hw/dataplane/virtio-blk.c include/char/baum.h include/char/msmouse.h qemu-char.c vl.c Resolve conflicts caused by header movements. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-03-05hw/arm_gic: Convert ARM GIC classes to use init/realizePeter Maydell1-7/+8
Convert the ARM GIC classes to use init/realize rather than SysBusDevice::init. (We have to do them all in one patch to avoid unconverted subclasses calling a nonexistent SysBusDevice init function in the base class and crashing.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2013-03-01hw: include hw header files with full pathsPaolo Bonzini1-3/+3
Done with this script: cd hw for i in `find . -name '*.h' | sed 's/^..//'`; do echo '\,^#.*include.*["<]'$i'[">], s,'$i',hw/&,' done | sed -i -f - `find . -type f` This is so that paths remain valid as files are moved. Instead, files in hw/dataplane are referenced with the relative path. We know they are not going to move to include/, and they are the only include files that are in subdirectories _and_ move. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-01-10Make all static TypeInfos constAndreas Färber1-1/+1
Since 39bffca2030950ef6efe57c2fac8327a45ae1015 (qdev: register all types natively through QEMU Object Model), TypeInfo as used in the common, non-iterative pattern is no longer amended with information and should therefore be const. Fix the documented QOM examples: sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h Since frequently the wrong examples are being copied by contributors of new devices, fix all types in the tree: sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c This also avoids to piggy-back these changes onto real functional changes or other refactorings. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-19misc: move include files to include/qemu/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-11hw/arm_gic_common: Correct GICC_PMR reset value for newer GICsPeter Maydell1-1/+3
The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-10-30hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMPPeter Maydell1-12/+19
Use LOG_GUEST_ERROR and LOG_UNIMP rather than hw_error() where appropriate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-30hw/armv7m_nvic: Implement byte/halfword access for NVIC SCB_SHPRx registersAndre Beckus1-30/+28
Implement byte/halfword read and write for the NVIC SCB_SHPRx (System Handler Priority Registers). Do this by removing SHPR word access from nvic_readl/writel and adding common code to hande all access sizes in nvic_sysreg_read/write. Because the "nvic_state *s" variable now needs to be declared in nvic_sysreg_read/write, the "void *opaque" parameter of nvic_readl/writel is changed to "nvic_state *s". Signed-off-by: Andre Beckus <mikemail98-qemu@yahoo.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity1-2/+2
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-12arm_gic: Rename gic_state to GICStatePeter Maydell1-3/+3
Rename the gic_state struct to match QEMU's coding style conventions for structure names, since the impending KVM-for-ARM patches will create another subclass of it. This patch was created using: sed -i 's/gic_state/GICState/g' hw/arm_gic.c hw/arm_gic_common.c \ hw/arm_gic_internal.h hw/armv7m_nvic.c Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-26hw/armv7m_nvic: Correctly register GIC region when setting up NVICMeador Inge1-1/+2
When setting up the NVIC memory regions the memory range 0x100..0xcff is aliased to an IO memory region that belongs to the ARM GIC. This aliased region should be added to the NVIC memory container, but the actual GIC IO memory region was being added instead. This mixup was causing the wrong IO memory access functions to be called when accessing parts of the NVIC memory. Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-13hw/armv7m_nvic: Fix incorrect default for num-irqs propertyPeter Maydell1-7/+14
Fix an incorrect default value for the num-irqs property (we were attempting to override it from the default set by the parent class but not succeeding, which meant that the lm3s6965evb model would assert on startup attempting to wire up nonexistent irq lines). Instead of trying to override the parent's Property array, we define an instance_init function which runs after default setup but before user property setting and can just fix up the default value in the gic_state struct. Reported-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/armv7m_nvic: Make the NVIC a freestanding classPeter Maydell1-12/+36
Rearrange the GIC and NVIC so both are straightforward subclasses of a common class, rather than having the NVIC source file textually include arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Move CPU interface memory region setup into arm_gic_initPeter Maydell1-1/+1
Remove more NVIC ifdefs by moving the code to setup the CPU interface memory regions into the GIC specific arm_gic_init() function rather than the gic_init() function. Rename the latter to more closely reflect what it's now actually doing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Add qdev property for GIC revisionPeter Maydell1-0/+2
GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/armv7m_nvic: Use MemoryRegions for NVIC specific registersPeter Maydell1-1/+73
Implement the NVIC specific register areas using a set of overlaid MemoryRegions in a container, rather than by having the arm_gic read/write functions use special purpose callbacks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Move NVIC specific reset to armv7m_nvic_resetPeter Maydell1-0/+7
Move the NVIC specific bits of reset to the NVIC's own reset function, rather than using ifdefs in the common arm_gic reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Remove the special casing of NCPU for the NVICPeter Maydell1-3/+2
Drop the special casing of NCPU=1 for the NVIC. This slightly increases the amount of memory used by its state structure, but removes some ifdeffery and means we can safely move the GIC state into a common subclass structure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC definePeter Maydell1-1/+0
Now all the A profile cores have been switched to use the standalone sysbus GIC, the only remaining code which #includes arm_gic.c is the v7M NVIC. The coupling is much closer here so it's not so easily disentangled. For now, add a comment about how arm_gic.c is compiled, and assume that the NVIC always includes arm_gic.c and the non-NVIC GIC is always compiled standalone. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make gic_reset a sysbus reset functionPeter Maydell1-0/+16
Make gic_reset a sysbus reset function, so we actually reset the GIC on system reset rather than only at init. For the NVIC this requires us also to implement reset of the SysTick. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make the GIC its own sysbus devicePeter Maydell1-0/+1
Compile arm_gic.c as a standalone C file to produce a self contained sysbus GIC device. Support the legacy usage by #include of the .c file by making those users #define LEGACY_INCLUDED_GIC, so we can convert them one by one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Move gic_get_current_cpu into arm_gic.cPeter Maydell1-7/+0
Move the gic_get_current_cpu() function into arm_gic.c. There are only two implementations: (1) "get the index of the currently executing CPU", used by all multicore GICs, and (2) "always 0", used by all GICs instantiated with a single CPU interface (the Realview board GIC and the v7M NVIC). So we can move this into the main GIC source file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Move NCPU definition to arm_gic.cPeter Maydell1-1/+0
Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-02-15qom: Unify type registrationAndreas Färber1-2/+2
Replace device_init() with generalized type_init(). While at it, unify naming convention: type_init([$prefix_]register_types) Also, type_init() is a function, so add preceding blank line where necessary and don't put a semicolon after the closing brace. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Anthony Liguori <anthony@codemonkey.ws> Cc: malc <av1474@comtv.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-03qdev: register all types natively through QEMU Object ModelAnthony Liguori1-14/+18
This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-27sysbus: apic: ioapic: convert to QEMU Object ModelAnthony Liguori1-7/+14
This converts three devices because apic and ioapic are subclasses of sysbus. Converting subclasses independently of their base class is prohibitively hard. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-17arm: make the number of GIC interrupts configurableMark Langsdorf1-8/+23
Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020, and create a configurable property for each defaulting to 96 and 64 (respectively) so that device modelers can set the value appropriately for their SoC. Other ARM processors also set their maximum number of used IRQs appropriately. Set the maximum theoretical number of GIC interrupts to 1020 and update the save/restore code to only use the appropriate number for each SoC. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> [Peter Maydell: fixed minor whitespace snafu] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-22arm_gic: convert to memory APIAvi Kivity1-1/+2
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-23Correct spelling of licensedMatthew Fernandez1-1/+1
Correct typos of "licenced" to "licensed". Reviewed-by: Stefan Weil <weil@mail.berlios.de> Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de> Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-04-22vmstate: port armv7m nvicJuan Quintela1-25/+14
Signed-off-by: Juan Quintela <quintela@redhat.com>
2011-03-21change all other clock references to use nanosecond resolution accessorsPaolo Bonzini1-4/+4
This was done with: sed -i 's/qemu_get_clock\>/qemu_get_clock_ns/' \ $(git grep -l 'qemu_get_clock\>' ) sed -i 's/qemu_new_timer\>/qemu_new_timer_ns/' \ $(git grep -l 'qemu_new_timer\>' ) after checking that get_clock and new_timer never occur twice on the same line. There were no missed occurrences; however, even if there had been, they would have been caught by the compiler. There was exactly one false positive in qemu_run_timers: - current_time = qemu_get_clock (clock); + current_time = qemu_get_clock_ns (clock); which is of course not in this patch. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2010-07-06savevm: Add DeviceState paramAlex Williamson1-1/+1
When available, we'd like to be able to access the DeviceState when registering a savevm. For buses with a get_dev_path() function, this will allow us to create more unique savevm id strings. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-05-02Fix missing '|' in '|=', spotted by clang analyzerBlue Swirl1-4/+4
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-27qdev: add return value to init() callbacks.Gerd Hoffmann1-1/+2
Sorry folks, but it has to be. One more of these invasive qdev patches. We have a serious design bug in the qdev interface: device init callbacks can't signal failure because the init() callback has no return value. This patch fixes it. We have already one case in-tree where this is needed: Try -device virtio-blk-pci (without drive= specified) and watch qemu segfault. This patch fixes it. With usb+scsi being converted to qdev we'll get more devices where the init callback can fail for various reasons. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-04Remove ARM NVIC initialization hackPaul Brook1-5/+0
The ARMv7-M NVIC device pokes itself into the CPU state. Now we have a proper device model we can have the CPU/SoC code do this. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-14ARM GIC qdev conversionPaul Brook1-52/+57
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-08Replace cpu_abort with hw_errorPaul Brook1-8/+7
Signed-off-by: Paul Brook <paul@codesourcery.com>
2008-09-17Fix warnings that would be caused by ld flag --warn-commonblueswir11-0/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5240 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-4/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-02Save/restore for stellaris boards.pbrook1-0/+26
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4824 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24Stellaris ethernet support.pbrook1-1/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3728 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-24ARMv7-M SysTick fix.pbrook1-4/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3727 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Break up vl.h.pbrook1-2/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-11ARMv7 support.pbrook1-0/+381
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
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