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2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi58-100/+100
Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21Merge tag 'pull-riscv-to-apply-20241220' of ↵Stefan Hajnoczi1-2/+6
https://github.com/alistair23/qemu into staging RISC-V PR for 10.0 * Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT # gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv # h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ # A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC # X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX # 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF # 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC # mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 # Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA # gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 # 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm # EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= # =0iQW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 20:54:00 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu: (39 commits) target/riscv: add support for RV64 Xiangshan Nanhu CPU target/riscv: add ssstateen target/riscv/tcg: hide warn for named feats when disabling via priv_ver target/riscv: Include missing headers in 'internals.h' target/riscv: Include missing headers in 'vector_internals.h' target/riscv: Check svukte is not enabled in RV32 target/riscv: Expose svukte ISA extension target/riscv: Check memory access to meet svukte rule target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Add svukte extension capability variable hw/riscv: Add the checking if DTB overlaps to kernel or initrd hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses hw/char/riscv_htif: Explicit little-endian implementation MAINTAINERS: Cover RISC-V HTIF interface tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format qtest: allow SPCR acpi table changes ... Conflicts: target/riscv/cpu.c Merge conflict with DEFINE_PROP_END_OF_LIST() removal. No Property array terminator is needed anymore. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé58-99/+99
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-12-20qom: Add TYPE_CONTAINER macroPeter Xu1-1/+1
Provide a macro for the container type across QEMU source tree, rather than hard code it every time. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-ID: <20241121192202.4155849-2-peterx@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-20hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 formatSia Jee Heng1-2/+6
Update the SPCR table to accommodate the SPCR Table revision 4 [1]. The SPCR table has been modified to adhere to the revision 4 format [2]. [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table [2]: https://github.com/acpica/acpica/pull/931 Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20241028015744.624943-3-jeeheng.sia@starfivetech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson16-17/+0
Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19hw/arm/armsse: Use device_class_set_props_nRichard Henderson1-4/+5
We must remove DEFINE_PROP_END_OF_LIST so the count is correct. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-17-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-15hw/arm: Constify all PropertyRichard Henderson18-22/+22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-14hw/ide/ahci: Extract TYPE_SYSBUS_AHCI into dedicated fileBernhard Beschow1-5/+5
Implement in dedicated file, just like TYPE_ICH9_AHCI. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241212110926.23548-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-14hw: Use pci_bus_add_fw_cfg_extra_pci_roots()Philippe Mathieu-Daudé1-1/+2
We want to remove fw_cfg_add_extra_pci_roots() which introduced PCI bus knowledge within the generic hw/nvram/fw_cfg.c file. Replace the calls by the pci_bus_add_fw_cfg_extra_pci_roots() which is a 1:1 equivalent, but using correct API. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241206181352.6836-6-philmd@linaro.org>
2024-12-12Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2-3/+3
* rust: better integration with clippy, rustfmt and rustdoc * rust: interior mutability types * rust: add a bit operations module * rust: first part of QOM rework * kvm: remove unnecessary #ifdef * clock: small cleanups, improve handling of Clock lifetimes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdZqFkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOzRwf/SYUD+CJCn2x7kUH/JG893jwN1WbJ # meGZ0PQDUpOZJFWg6T4g0MuW4O+Wevy2pF4SfGojgqaYxKBbTQVkeliDEMyNUxpr # vSKXego0K3pkX3cRDXNVTaXFbsHsMt/3pfzMQM6ocF9qbL+Emvx7Og6WdAcyJ4hc # lA17EHlnrWKUSnqN/Ow/pZXsa4ijCklXFFh4barfbdGVhMQc2QekUU45GsP2AvGT # NkXTQC05HqxBaAIDeSxbprDSzNihyT71dAooVoxqKboprPu5uoUSJwgaD8rADPr4 # EOfsz61V4mji+DWDcIzTtYoAdY41vVXI9lvCKOcCFkimA29xO0W6P7mG2w== # =JSh5 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 09:57:29 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (49 commits) rust: qom: change the parent type to an associated type rust: qom: split ObjectType from ObjectImpl trait rust: qom: move bridge for TypeInfo functions out of pl011 rust: qdev: move bridge for realize and reset functions out of pl011 rust: qdev: move device_class_init! body to generic function, ClassInitImpl implementation to macro rust: qom: move ClassInitImpl to the instance side rust: qom: convert type_info! macro to an associated const rust: qom: rename Class trait to ClassInitImpl rust: qom: add default definitions for ObjectImpl rust: add a bit operation module rust: add bindings for interrupt sources rust: define prelude rust: cell: add BQL-enforcing RefCell variant rust: cell: add BQL-enforcing Cell variant bql: check that the BQL is not dropped within marked sections qom/object: Remove type_register() script/codeconverter/qom_type_info: Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic ui: Replace type_register() with type_register_static() target/xtensa: Replace type_register() with type_register_static() target/sparc: Replace type_register() with type_register_static() ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12Merge tag 'pull-request-2024-12-11' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi1-1/+8
staging * Add compat machines for QEMU 10.0 * Add s390x CPU model for the gen17 mainframe * Convert some more avocado tests to the new functional framework * Some minor clean-ups for functional tests # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmdZUu0RHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVpzBAAo/xldyDvEBkQiHpw7YF5x6dipSdQmgbL # 02Qq1p2A7LxGK7uv6HBtOwhxk2eB0F+o8ZNt79u6QJmrI7Anme40B6GRXKHpm+Nn # 2zn6xzBKnKJSjI/mr3zNqQwCb+q68hL+0N9oNSlbl42uElnMNMr1elkW7W+YT70d # w+P5UzV2AuvjC6ML1R6ULwJHdeoklAk87g7l3Ns5z8CPFCV3yMOzGHqgpYQdYl+U # Cx0CT/xqkfoyustkbPSCUGDzZbLQLMHcCgGX9DVLUmP8I6U1MeZC3HIxYdI4ofX/ # ApFQ4ThMV5f0A6hnn2TRrP+74He6wjYkB3RUjXtchVizWm1FZhNNa//cWvoEmCFU # ufwuAFNvTodli0/47GEmwu8t/jqXJ1SeC50VAPyzxpedJwkgaMAZiYAlDO/oxIY1 # BCNR5bDjf4pAzguHG4FnPxaOcb5UT+V+sukQMvxa03TGrTp2/U9sanCVVdGPOovI # sf/nXsK6jYe1mvinLF9wTyAjjkXqboqfgRabQi2DRgP/FMKseGapy4fOOXzj5Flv # 5FSdyzm4/3fnb2fl1cWSNqPCLwAtmPWx0weu7PBbhP7AwNEXbpJcHmjtJwxL5Slx # c+qazS6lbeBphPlToEqhibOZAxMM6QYvFxhL8Ut36vyEBbO/LAjy9+od9/jb8QCd # ijtWjauVpHc= # =BG+s # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 03:53:01 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-12-11' of https://gitlab.com/thuth/qemu: (26 commits) tests/functional: remove pointless with statement tests/functional: remove unused system imports tests/functional: Convert the cubieboard avocado tests tests/functional: Convert the smdkc210 avocado test tests/functional: Convert the emcraft_sf2 avocado test tests/functional: Convert the xlnx_versal_virt avocado test MAINTAINERS: Cover the tests/functional/test_sh4eb_r2d.py file tests/functional: Bump the timeout of the sh4_tuxrun test s390x/cpumodel: gen17 model s390x/cpumodel: Add PLO-extension facility s390x/cpumodel: correct PLO feature wording s390x/cpumodel: Add Sequential-Instruction-Fetching facility s390x/cpumodel: add Ineffective-nonconstrained-transaction facility s390x/cpumodel: add Vector-Packed-Decimal-Enhancement facility 3 s390x/cpumodel: add Miscellaneous-Instruction-Extensions Facility 4 s390x/cpumodel: add Vector Enhancements facility 3 s390x/cpumodel: add Concurrent-functions facility support linux-headers: Update to Linux 6.13-rc1 s390x/cpumodel: Add ptff Query Time-Stamp Event (QTSE) support s390x/cpumodel: add msa13 subfunctions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-11hw: add compat machines for 10.0Cornelia Huck1-1/+8
Add 10.0 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241126103005.3794748-3-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11aspeed/soc: Support eMMC for AST2700Jamin Lin1-0/+15
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1 slot and registers base address is start at 0x1209_0000 and its interrupt is connected to GICINT 15. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-11aspeed/soc: Support SDHCI for AST2700Jamin Lin1-0/+20
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1 slot and registers base address is start at 0x1408_0000 and its interrupt is connected to GICINT133_INTC at bit 1. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-11hw:sdhci: Introduce a new "capareg" class member to set the different ↵Jamin Lin2-5/+5
Capability Registers Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support for AST2700. Introduce a new "capareg" class member whose data type is uint_64 to set the different Capability Registers to all ASPEED SOCs. The value of Capability Register is "0x0000000001e80080" for AST2400 and AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-11hw/arm/aspeed: Fix coding styleJamin Lin1-1/+2
Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-11arm: Remove tacoma-bmc machineCédric Le Goater1-28/+0
Removal was scheduled for 10.0. Use the rainier-bmc machine or the ast2600-evb as a replacement. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241119071352.515790-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-10arm: Replace type_register() with type_register_static()Zhao Liu2-3/+3
Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20241029085934.2799066-2-zhao1.liu@intel.com
2024-11-05Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell1-2/+1
into staging virtio,pc,pci: features, fixes, cleanups CXL now can use Generic Port Affinity Structures. CXL now allows control of link speed and width vhost-user-blk now supports live resize, by means of a new device-sync-config command amd iommu now supports interrupt remapping pcie devices now report extended tag field support intel_iommu dropped support for Transient Mapping, to match VTD spec arch agnostic ACPI infrastructure for vCPU Hotplug Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmcpNqUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRp/2oH/0qO33prhDa48J5mqT9NuJzzYwp5QHKF9Zjv # fDAplMUEmfxZIEgJchcyDWPYTGX2geT4pCFhRWioZMIR/0JyzrFgSwsk1kL88cMh # 46gzhNVD6ybyPJ7O0Zq3GLy5jo7rlw/n+fFxKAuRCzcbK/fmH8gNC+RwW1IP64Na # HDczYilHUhnO7yKZFQzQNQVbK4BckrG1bu0Fcx0EMUQBf4V6x7GLOrT+3hkKYcr6 # +DG5DmUmv20or/FXnu2Ye+MzR8Ebx6JVK3A3sXEE4Ns2CCzK9QLzeeyc2aU13jWN # OpZ6WcKF8HqYprIwnSsMTxhPcq0/c7TvrGrazVwna5RUBMyjjvc= # =zSX4 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 21:03:33 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (65 commits) intel_iommu: Add missed reserved bit check for IEC descriptor intel_iommu: Add missed sanity check for 256-bit invalidation queue intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL hw/acpi: Update GED with vCPU Hotplug VMSD for migration tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35} hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states qtest: allow ACPI DSDT Table changes hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug hw/pci: Add parenthesis to PCI_BUILD_BDF macro hw/cxl: Ensure there is enough data to read the input header in cmd_get_physical_port_state() hw/cxl: Ensure there is enough data for the header in cmd_ccls_set_lsa() hw/cxl: Check that writes do not go beyond end of target attributes hw/cxl: Ensuring enough data to read parameters in cmd_tunnel_management_cmd() hw/cxl: Avoid accesses beyond the end of cel_log. hw/cxl: Check the length of data requested fits in get_log() hw/cxl: Check enough data in cmd_firmware_update_transfer() hw/cxl: Check input length is large enough in cmd_events_clear_records() hw/cxl: Check input includes at least the header in cmd_features_set_feature() hw/cxl: Check size of input data to dynamic capacity mailbox commands hw/cxl/cxl-mailbox-util: Fix output buffer index update when retrieving DC extents ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-04hw/acpi: Generic Port Affinity Structure supportJonathan Cameron1-1/+1
These are very similar to the recently added Generic Initiators but instead of representing an initiator of memory traffic they represent an edge point beyond which may lie either targets or initiators. Here we add these ports such that they may be targets of hmat_lb records to describe the latency and bandwidth from host side initiators to the port. A discoverable mechanism such as UEFI CDAT read from CXL devices and switches is used to discover the remainder of the path, and the OS can build up full latency and bandwidth numbers as need for work and data placement decisions. Acked-by: Markus Armbruster <armbru@redhat.com> Tested-by: "Huang, Ying" <ying.huang@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916174122.1843197-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-11-04acpi/pci: Move Generic Initiator object handling into acpi/pci.*Jonathan Cameron1-1/+0
Whilst ACPI SRAT Generic Initiator Afinity Structures are able to refer to both PCI and ACPI Device Handles, the QEMU implementation only implements the PCI Device Handle case. For now move the code into the existing hw/acpi/pci.c file and header. If support for ACPI Device Handles is added in the future, perhaps this will be moved again. Also push the struct AcpiGenericInitiator down into the c file as not used outside pci.c. Suggested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: "Huang, Ying" <ying.huang@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240916171017.1841767-7-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-11-04aspeed: Don't set always boot properties of the emmc deviceCédric Le Goater1-3/+13
Commit e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") added support to boot from an eMMC device by setting the boot properties of the eMMC device. This change made the assumption that the device always has boot areas. However, if the machine boots from the flash device (or -kernel) and uses an eMMC device without boot areas, support would be broken. This impacts the ast2600-evb machine which can choose to boot from flash or eMMC using the "boot-emmc" machine option. To provide some flexibility for Aspeed machine users to use different flavors of eMMC devices (with or without boot areas), do not set the eMMC device boot properties when the machine is not configured to boot from eMMC. However, this approach makes another assumption about eMMC devices, namely that eMMC devices from which the machine does not boot do not have boot areas. A preferable alternative would be to add support for user creatable eMMC devices and define the device boot properties on the QEMU command line : -blockdev node-name=emmc0,driver=file,filename=mmc-ast2600-evb.raw \ -device emmc,bus=sdhci-bus.2,drive=emmc0,boot-partition-size=1048576,boot-config=8 This is a global change requiring more thinking. Nevertheless, in the case of the ast2600-evb machine booting from an eMMC device and when default devices are created, the proposed change still makes sense since the device is required to have boot areas. Cc: Jan Luebbe <jlu@pengutronix.de> Fixes: e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") Signed-off-by: Cédric Le Goater <clg@redhat.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Jan Luebbe <jlu@pengutronix.de> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04aspeed: Support create flash devices via command line for AST1030Jamin Lin1-10/+12
Add a "if-statement" in aspeed_minibmc_machine_init function. If users add "-nodefaults" in command line, the flash devices should be created by users setting. Otherwise, the flash devices are created at machine init. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04aspeed/soc: Support RTC for AST2700Jamin Lin1-0/+11
The RTC controller between AST2600 and AST2700 are identical. Add RTC model for AST2700 RTC support. The RTC controller registers base address is start at 0x12C0_F000 and its alarm interrupt is connected to GICINT13. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculationPeter Maydell1-4/+3
When calculating the index into the GIC's GPIO array for per-CPU interrupts, we have to start with the number of SPIs. The code currently hard-codes this to 'NUM_IRQS = 256'. However the number of SPIs is set separately and implicitly by the value of AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is what we set the GIC num-irq property to). Define AST2700_MAX_IRQ as the total number of SPIs; this brings AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the number of SPIs not including the 32 internal interrupts. We can then use AST2700_MAX_IRQ instead of the hardcoded 256. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitionsPeter Maydell1-9/+10
Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Note that bsa.h defines these values as INTID values, which are all 16 greater than the PPI values that we were previously using. So we refactor the code to use INTID-based values to match that. This is the same thing we did in commit d40ab068c07d9 for sbsa-ref. It removes the "same constant, different values" confusion where this board code and bsa.h both define an ARCH_GIC_MAINT_IRQ, and allows us to use symbolic names for the timer interrupt IDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04hw/arm: enable at24c with aspeedPatrick Leis1-0/+1
Enable AT24C with ASPEED in the KConfig because the boards build this device. Signed-off-by: Patrick Leis <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-10-29arm/kvm: add support for MTECornelia Huck1-30/+42
Extend the 'mte' property for the virt machine to cover KVM as well. For KVM, we don't allocate tag memory, but instead enable the capability. If MTE has been enabled, we need to disable migration, as we do not yet have a way to migrate the tags as well. Therefore, MTE will stay off with KVM unless requested explicitly. [gankulkarni: This patch is rework of commit b320e21c48 which broke TCG since it made the TCG -cpu max report the presence of MTE to the guest even if the board hadn't enabled MTE by wiring up the tag RAM. This meant that if the guest then tried to use MTE QEMU would segfault accessing the non-existent tag RAM.] Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com> Message-id: 20241008114302.4855-1-gankulkarni@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-25Merge tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu into ↵Peter Maydell2-5/+17
staging aspeed queue: * Fixed GPIO interrupt status when in index mode * Added GPIO support for the AST2700 SoC and specific test cases * Fixed crypto controller (HACE) Accumulative hash function * Converted Aspeed machine avocado tests to the new functional framework. SDK tests still to be addressed. * Fixed issue in the SSI controller when doing writes in user mode * Added support for the WRSR2 register of Winbond flash devices * Added SFDP table for the Windbond w25q80bl flash device * Changed flash device models for the ast1030-a1 EVB # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmcZ6MIACgkQUaNDx8/7 # 7KFQPA//RTxi1PmCDlzd1ffzMWEadD3CpGLJ4RgEeZpNtkx6IF2uFFBdlNgjTSmD # B8FdIOVb8qo2omXahKIVIgoKbGgn3U3jciH67D/x4Jyp8IhW6n5XwZzKNJ7kLVHX # IluGmlvqNumSKl3vxsLvprC0ojRiO/SfWkzS6VOwoFPM7uNDTybQicWBBoy3Jh3e # VVlMwIeKHMQVJGpI8PQbtnFZO4HaMqWwlo0EoIJji59fdyWULLvrXzH9YhzwFVjQ # oCNvJUBLfxLse7c13cm/LuNmw+IQtLC5OztsOOtv1XZ1MruhJ7t316eGsQEpeWcD # Yy5RK4mIBJMExu9oxcKOqgSznQSgenvNGWg6Z9FyyKGciylafnE8GeT35WObumyD # v9gzgeLcw5DgvDgQXaYi4IkKyezaHoE3HPbFdBEZHBt8tn5pPGmXM0lEWL5xQ5B8 # h6HphjxIlFxeHIxYenLJowLBMOt8aFXzGboF2XCLrx19OC2zvoo7klCbFeAfZpvQ # JMXP+GsQIe7fnBMbyXGrJh9q+/7tKR4ivtTV/vnSF0FPtyzxdoSrYsUA4SZqSWvI # ONz62p+zlE/oXBUIaFnC2Ea41YwJ7mDbmcSU1dFxmE0xRVmoYlUocoeS2VOUmTH0 # CMgEcmMXQG0vx8nipQbScbuWRCBlf0YwJ7Y7stgI8HabmsMMbIg= # =DqCH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Oct 2024 07:27:14 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20241024' of https://github.com/legoater/qemu: test/qtest/aspeed_smc-test: Fix coding style hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVB hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB. hw/block/m25p80: Add SFDP table for w25q80bl flash hw/block:m25p80: Support write status register 2 command (0x31) for w25q01jvq hw/block:m25p80: Fix coding style aspeed/smc: Fix write incorrect data into flash in user mode tests/functional: Convert most Aspeed machine tests hw/misc/aspeed_hace: Fix SG Accumulative hashing tests/qtest:ast2700-gpio-test: Add GPIO test case for AST2700 aspeed/soc: Support GPIO for AST2700 aspeed/soc: Correct GPIO irq 130 for AST2700 hw/gpio/aspeed: Add AST2700 support hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode hw/gpio/aspeed: Support different memory region ops hw/gpio/aspeed: Support to set the different memory size hw/gpio/aspeed: Fix coding style Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-24hw/arm/aspeed: Correct fmc_model w25q80bl for ast1030-a1 EVBJamin Lin1-1/+1
Currently, the default fmc_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of fmc_cs0 and fmc_cs1 were "w25q80bl" and "w25q256", respectively. The size of w25q80bl is 1MB and the size of w25q256 is 32MB. The fmc_cs0 was connected to AST1030 A1 internal flash and the fmc_cs1 was connected to external flash. The internal flash could not be changed because it was placed into AST1030 A1 chip. Users only can change fmc_cs1 external flash. So far, only supports to set the default fmc_model for all chip select pins. In other words, users cannot set the different default flash model for fmc_cs0 and fmc_cs1, respectively. Correct fmc_model default flash to w25q80bl the same as AST1030 A1 internal flash for ast1030-a1 EVB. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-10-24hw/arm/aspeed: Correct spi_model w25q256 for ast1030-a1 EVB.Jamin Lin1-1/+1
Currently, the default spi_model was "sst25vf032b" whose size was 4MB for ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB, ASPEED shipped default flash of spi1 and spi2 were w25q256 whose size was 32MB. Correct spi_model default flash to w25q256 for ast1030-a1 EVB. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-10-24aspeed/soc: Support GPIO for AST2700Jamin Lin1-0/+13
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base address is start at 0x14C0_B000 and its address space is 0x1000. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-10-24aspeed/soc: Correct GPIO irq 130 for AST2700Jamin Lin1-3/+2
The register set of GPIO have a significant change since AST2700. Each GPIO pin has their own individual control register and users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in the same one control register. AST2700 does not have GPIO18_XXX registers for GPIO 1.8v, removes ASPEED_DEV_GPIO_1_8V. It is enough to only have ASPEED_DEV_GPIO device in AST2700. The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at bit 18. Therefore, correct GPIO irq 130. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-10-21replace error_setg(&error_fatal, ...) with error_report()Tudor Gheorghiu4-11/+9
According to include/qapi/error.h: * Please don't error_setg(&error_fatal, ...), use error_report() and * exit(), because that's more obvious. Patch updates all instances of error_setg(&error_fatal, ...) with error_report(...), adds the explicit exit(1) and removes redundant return statements. Signed-off-by: Tudor Gheorghiu <tudor.reda@gmail.com> Suggested-by: Thomas Huth <thuth@redhat.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2587 Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> (Mjt: also fold __func__ to previous line)
2024-10-15hw/arm/xilinx_zynq: Add various missing unimplemented devicesChao Liu1-0/+70
Add unimplemented-device blocks to the xilinx_zynq board corresponding to various devices documented in the TRM and in the device tree. See: ug585-Zynq-7000-TRM manual B.3 (Module Summary) Signed-off-by: Chao Liu <chao.liu@yeah.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message. Removed the clearing of the ignore_memory_transaction_failures flag] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-15hw/block: Remove eccPeter Maydell1-1/+0
The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices, which we have removed, so it is now completely unused. Note that hw/misc/eccmemctl.c does not in fact use any of the code frome ecc.c, so that KConfig dependency was incorrect. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241003140010.1653808-6-peter.maydell@linaro.org
2024-10-15hw/arm: Add SPI to Allwinner A10Strahinja Jankovic2-0/+9
The Allwinner A10 SPI controller is added to the Allwinner A10 description, so it is available when Cubieboard is emulated. Update the documentation for Cubieboard to indicate SPI availability. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20241001221349.8319-3-strahinja.p.jankovic@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-15hw/misc: Create STM32L4x5 SYSCFG clockInès Varhol1-0/+2
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the corresponding clock from STM32L4x5 RCC. Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20241003081105.40836-2-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-15hw/arm/stm32f405: Add RCC device to stm32f405 SoCRomán Cárdenas Rodríguez2-1/+12
Add the reset and clock controller device to the stm32f405 SoC. Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com> [PMM: tweak commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-15hw/arm/omap1: Remove unused omap_uwire_attach() methodPhilippe Mathieu-Daudé1-21/+8
The recently removed 'cheetah' machine was the single user of the omap_uwire_attach() method. Remove it altogether with the uWireSlave structure. Replace the send/receive callbacks by Unimplemented logging. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-11rust: add PL011 device modelPaolo Bonzini1-10/+20
This commit adds a re-implementation of hw/char/pl011.c in Rust. How to build: 1. Configure a QEMU build with: --enable-system --target-list=aarch64-softmmu --enable-rust 2. Launching a VM with qemu-system-aarch64 should use the Rust version of the pl011 device Co-authored-by: Junjie Mao <junjie.mao@intel.com> Co-authored-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Junjie Mao <junjie.mao@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Link: https://lore.kernel.org/r/6ec1d4fb8db2a1d7ba94c73e65d9770371b7857d.1727961605.git.manos.pitsidianakis@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell10-18/+18
* pc: Add a description for the i8042 property * kvm: support for nested FRED * tests/unit: fix warning when compiling test-nested-aio-poll with LTO * kvm: refactoring of VM creation * target/i386: expose IBPB-BRTYPE and SBPB CPUID bits to the guest * hw/char: clean up serial * remove virtfs-proxy-helper * target/i386/kvm: Report which action failed in kvm_arch_put/get_registers * qom: improvements to object_resolve_path*() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmb++MsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPVnwf/cdvfxvDm22tEdlh8vHlV17HtVdcC # Hw334M/3PDvbTmGzPBg26lzo4nFS6SLrZ8ETCeqvuJrtKzqVk9bI8ssZW5KA4ijM # nkxguRPHO8E6U33ZSucc+Hn56+bAx4I2X80dLKXJ87OsbMffIeJ6aHGSEI1+fKVh # pK7q53+Y3lQWuRBGhDIyKNuzqU4g+irpQwXOhux63bV3ADadmsqzExP6Gmtl8OKM # DylPu1oK7EPZumlSiJa7Gy1xBqL4Rc4wGPNYx2RVRjp+i7W2/Y1uehm3wSBw+SXC # a6b7SvLoYfWYS14/qCF4cBL3sJH/0f/4g8ZAhDDxi2i5kBr0/5oioDyE/A== # =/zo4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Oct 2024 21:04:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) qom: update object_resolve_path*() documentation qom: set *ambiguous on all paths qom: rename object_resolve_path_type() "ambiguousp" target/i386/kvm: Report which action failed in kvm_arch_put/get_registers kvm: Allow kvm_arch_get/put_registers to accept Error** accel/kvm: refactor dirty ring setup minikconf: print error entirely on stderr 9p: remove 'proxy' filesystem backend driver hw/char: Extract serial-mm hw/char/serial.h: Extract serial-isa.h hw: Remove unused inclusion of hw/char/serial.h target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guest kvm: refactor core virtual machine creation into its own function kvm/i386: replace identity_base variable with a constant kvm/i386: refactor kvm_arch_init and split it into smaller functions kvm: replace fprintf with error_report()/printf() in kvm_init() kvm/i386: fix return values of is_host_cpu_intel() kvm/i386: make kvm_filter_msr() and related definitions private to kvm module hw/i386/pc: Add a description for the i8042 property tests/unit: remove block layer code from test-nested-aio-poll ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/Kconfig # hw/arm/pxa2xx.c
2024-10-03hw/arm: xenpvh: Enable PCI for ARM PVHEdgar E. Iglesias1-0/+14
Enable PCI support for the ARM Xen PVH machine. Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-10-03hw/xen: xenpvh: Disable buffered IOREQs for ARMEdgar E. Iglesias1-0/+3
Add a way to enable/disable buffered IOREQs for PVH machines and disable them for ARM. ARM does not support buffered IOREQ's nor the legacy way to map IOREQ info pages. See the following for more details: https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=2fbd7e609e1803ac5e5c26e22aa8e4b5a6cddbb1 https://xenbits.xen.org/gitweb/?p=xen.git;a=blob;f=xen/arch/arm/ioreq.c;h=2e829d2e7f3760401b96fa7c930e2015fb1cf463;hb=HEAD#l138 Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-10-03hw/char: Extract serial-mmBernhard Beschow11-20/+20
hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's move the latter into its own module which makes the dependencies more obvious and the code more tidy. The includes and the dependencies have been converted mechanically except in the hw/char directories which were updated manually. The result was compile-tested. Now, only hw/char makes direct use of TYPE_SERIAL: # grep -r -e "select SERIAL" | grep -v SERIAL_ hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL # grep -r -e "/serial\\.h" include/hw/char/serial-mm.h:#include "hw/char/serial.h" hw/char/serial-pci-multi.c:#include "hw/char/serial.h" hw/char/serial.c:#include "hw/char/serial.h" hw/char/serial-isa.c:#include "hw/char/serial.h" hw/char/serial-pci.c:#include "hw/char/serial.h" Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-4-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-01hw/arm: Remove omap2.cPeter Maydell2-2716/+0
The users of the OMAP2 SoC emulation have been removed, so we can delete omap2.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903160751.4100218-38-peter.maydell@linaro.org
2024-10-01hw/misc: Remove cbusPeter Maydell1-14/+0
The devices in hw/misc/cbus.c were used only by the now-removed nseries machine types, so they can be removed. As this is the last use of the CONFIG_NSERIES define we can remove that from KConfig now. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240903160751.4100218-27-peter.maydell@linaro.org
2024-10-01hw/arm: Remove 'n800' and 'n810' machinesPeter Maydell2-1474/+0
Remove the 'n800' and 'n810' machine types, which modelled Nokia internet tablets. These were deprecated in 9.0 and so we can remove them for 9.2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903160751.4100218-26-peter.maydell@linaro.org [PMM: added removal of arm-n800-machine.c post-review]
2024-10-01hw/arm: Remove pxa2xx_picPeter Maydell3-371/+0
Remove the pxa2xx-specific interrupt controller device. As this is the last user of the pxa.h header file and the CONFIG_PXA2XX define we can remove those too. This completes the removal of the pxa2xx specific code. We leave: * pxa2xx_timer -- still used by the Collie board (strongarm) * the definitions of the CPUs themselves in target/arm (still usable by linux-user mode) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240903160751.4100218-23-peter.maydell@linaro.org
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