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2023-01-12hw/arm/z2: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-2/+4
IEC binary prefixes ease code review: the unit is explicit. Add the FLASH_SECTOR_SIZE definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-12-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/omap_sx1: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-16/+17
IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/omap_sx1: Remove unused 'total_ram' definitionsPhilippe Mathieu-Daudé1-2/+0
The total_ram_v1/total_ram_v2 definitions were never used. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/musicpal: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-3/+6
IEC binary prefixes ease code review: the unit is explicit. Add the FLASH_SECTOR_SIZE definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/mainstone: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-8/+10
IEC binary prefixes ease code review: the unit is explicit. Add the FLASH_SECTOR_SIZE definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/gumstix: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-13/+14
IEC binary prefixes ease code review: the unit is explicit. Add definitions for RAM / Flash / Flash blocksize. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-7-philmd@linaro.org Message-Id: <20200223231044.8003-3-philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/gumstix: Improve documentationPhilippe Mathieu-Daudé1-2/+4
Add a comment describing the Connex uses a Numonyx RC28F128J3F75 flash, and the Verdex uses a Micron RC28F256P30TFA. Correct the Verdex machine description (we model the 'Pro' board). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-6-philmd@linaro.org Message-Id: <20200223231044.8003-3-philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/collie: Simplify flash creation using for() loopPhilippe Mathieu-Daudé1-10/+7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/collie: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé1-6/+10
IEC binary prefixes ease code review: the unit is explicit. Add definitions for RAM / Flash / Flash blocksize. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/pxa2xx: Simplify pxa270_init()Philippe Mathieu-Daudé5-16/+10
Since pxa270_init() must map the device in the system memory, there is no point in passing get_system_memory() by argument. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/pxa2xx: Simplify pxa255_init()Philippe Mathieu-Daudé3-4/+5
Since pxa255_init() must map the device in the system memory, there is no point in passing get_system_memory() by argument. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230109115316.2235-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm: Allwinner A10 enable SPL load from MMCStrahinja Jankovic2-0/+23
This patch enables copying of SPL from MMC if `-kernel` parameter is not passed when starting QEMU. SPL is copied to SRAM_A. The approach is reused from Allwinner H3 implementation. Tested with Armbian and custom Yocto image. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-7-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm: Add AXP209 to CubieboardStrahinja Jankovic2-0/+7
SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221226220303.14420-6-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12{hw/i2c,docs/system/arm}: Allwinner TWI/I2C EmulationStrahinja Jankovic3-1/+20
This patch implements Allwinner TWI/I2C controller emulation. Only master-mode functionality is implemented. The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is first part enabling the TWI/I2C bus operation. Since both Allwinner A10 and H3 use the same module, it is added for both boards. Docs are also updated for Cubieboard and Orangepi-PC board to indicate I2C availability. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/misc: Allwinner A10 DRAM Controller EmulationStrahinja Jankovic2-0/+8
During SPL boot several DRAM Controller registers are used. Most important registers are those related to DRAM initialization and calibration, where SPL initiates process and waits until certain bit is set/cleared. This patch adds these registers, initializes reset values from user's guide and updates state of registers as SPL expects it. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/misc: Allwinner-A10 Clock Controller Module EmulationStrahinja Jankovic2-0/+8
During SPL boot several Clock Controller Module (CCM) registers are read, most important are PLL and Tuning, as well as divisor registers. This patch adds these registers and initializes reset values from user's guide. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm: Add Olimex H405Felipe Balbi3-0/+74
Olimex makes a series of low-cost STM32 boards. This commit introduces the minimum setup to support SMT32-H405. See [1] for details [1] https://www.olimex.com/Products/ARM/ST/STM32-H405/ Signed-off-by: Felipe Balbi <balbi@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20221230145733.200496-3-balbi@kernel.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-12hw/arm/stm32f405: correctly describe the memory layoutFelipe Balbi1-0/+8
STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled Memory) at a different base address. Correctly describe the memory layout to give existing FW images a chance to run unmodified. Reviewed-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Felipe Balbi <balbi@kernel.org> Message-id: 20221230145733.200496-2-balbi@kernel.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX7D: Connect IRQs to GPIO devices.Jean-Christophe Dubois1-1/+30
IRQs were not associated to the various GPIO devices inside i.MX7D. This patch brings the i.MX7D on par with i.MX6. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 20221226101418.415170-1-jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX6UL: Add a specific GPT timer instance for the i.MX6ULJean-Christophe Dubois1-1/+1
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05i.MX7D: Connect GPT timers to IRQJean-Christophe Dubois1-0/+10
So far the GPT timers were unable to raise IRQs to the processor. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/smmu-common: Avoid using inlined functions with external linkagePhilippe Mathieu-Daudé1-7/+6
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)") and building with -Wall we get: hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline] hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, ^ static None of our code base require / use inlined functions with external linkage. Some places use internal inlining in the hot path. These two functions are certainly not in any hot path and don't justify any inlining, so these are likely oversights rather than intentional. Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20221216214924.4711-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scopePhilippe Mathieu-Daudé1-1/+1
This function is not used anywhere outside this file, so we can make the function "static void". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20221216214924.4711-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/nseries: Silent -Wmissing-field-initializers warningPhilippe Mathieu-Daudé1-6/+4
Silent when compiling with -Wextra: ../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers] { NULL } ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221220142520.24094-4-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-05hw/arm/nseries: Constify various read-only arraysPhilippe Mathieu-Daudé1-9/+9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221220142520.24094-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-21hw: Add compat machines for 8.0Cornelia Huck1-1/+8
Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr. Reviewed-by: Cédric Le Goater <clg@kaod.org> [ppc] Reviewed-by: Thomas Huth <thuth@redhat.com> [s390x] Reviewed-by: Greg Kurz <groug@kaod.org> [ppc] Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20221212152145.124317-2-cohuck@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2022-12-15Merge tag 'pull-target-arm-20221215-1' of ↵Peter Maydell4-47/+184
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue:  * hw/arm/virt: Add properties to allow more granular configuration of use of highmem space  * target/arm: Add Cortex-A55 CPU  * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement  * Implement FEAT_EVT  * Some 3-phase-reset conversions for Arm GIC, SMMU  * hw/arm/boot: set initrd with #address-cells type in fdt  * hw/misc: Move some arm-related files from specific_ss into softmmu_ss  * Restrict arm_cpu_exec_interrupt() to TCG accelerator # gpg: Signature made Thu 15 Dec 2022 17:38:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20221215-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits) target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator hw/misc: Move some arm-related files from specific_ss into softmmu_ss hw/arm/boot: set initrd with #address-cells type in fdt hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset target/arm: Report FEAT_EVT for TCG '-cpu max' target/arm: Implement HCR_EL2.TID4 traps target/arm: Implement HCR_EL2.TICAB,TOCU traps target/arm: Implement HCR_EL2.TTLBOS traps target/arm: Implement HCR_EL2.TTLBIS traps target/arm: Allow relevant HCR bits to be written for FEAT_EVT hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement target/arm: Add Cortex-A55 CPU ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/boot: set initrd with #address-cells type in fdtSchspa Shi1-4/+6
We use 32bit value for linux,initrd-[start/end], when we have loader_start > 4GB, there will be a wrong initrd_start passed to the kernel, and the kernel will report the following warning. [ 0.000000] ------------[ cut here ]------------ [ 0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ... [ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244 [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 6.1.0-rc3-13250-g30a0b95b1335-dirty #28 [ 0.000000] Hardware name: Horizon Sigi Virtual development board (DT) [ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.000000] pc : arm64_memblock_init+0x158/0x244 [ 0.000000] lr : arm64_memblock_init+0x158/0x244 [ 0.000000] sp : ffff800009273df0 [ 0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000 [ 0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000 [ 0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000 [ 0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020 [ 0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261 [ 0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000 [ 0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000 [ 0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69 [ 0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88 [ 0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056 [ 0.000000] Call trace: [ 0.000000] arm64_memblock_init+0x158/0x244 [ 0.000000] setup_arch+0x164/0x1cc [ 0.000000] start_kernel+0x94/0x4ac [ 0.000000] __primary_switched+0xb4/0xbc [ 0.000000] ---[ end trace 0000000000000000 ]--- [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000001000000000-0x0000001007ffffff] This doesn't affect any machine types we currently support, because for all of our machine types the RAM starts well below the 4GB mark, but it does demonstrate that we're not currently writing the device-tree properties quite as intended. To fix it, we can change it to write these values to the dtb using a type width matching #address-cells. This is the intended size for these dtb properties, and is how u-boot, for instance, writes them, although in practice the Linux kernel will cope with them being any width as long as they're big enough to fit the value. Signed-off-by: Schspa Shi <schspa@gmail.com> Message-id: 20221129160724.75667-1-schspa@gmail.com [PMM: tweaked commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase resetPeter Maydell1-4/+8
Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy reset method doesn't do anything that's invalid in the hold phase, so the conversion only requires changing it to a hold phase method, and using the 3-phase versions of the "save the parent reset method and chain to it" code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org
2022-12-15hw/arm: Convert TYPE_ARM_SMMU to 3-phase resetPeter Maydell1-3/+4
Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method doesn't do anything that's invalid in the hold phase, so the conversion is simple and not a behaviour change. Note that we must convert this base class before we can convert the TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable handles "chain to parent class reset" when the base class is 3-phase and the subclass is still using legacy reset, but not the other way around. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org
2022-12-15target/arm: Add Cortex-A55 CPUTimofey Kutergin1-0/+1
The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular it supports the Privileged Access Never (PAN) feature. Add a model of this CPU, so you can use a CPU type on the virt board that models a specific real hardware CPU, rather than having to use the QEMU-specific "max" CPU type. Signed-off-by: Timofey Kutergin <tkutergin@gmail.com> Message-id: 20221121150819.2782817-1-tkutergin@gmail.com [PMM: tweaked commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: build SMBIOS 19 tableMihai Carabas1-1/+7
Use the base_memmap to build the SMBIOS 19 table which provides the address mapping for a Physical Memory Array (from spec [1] chapter 7.20). This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5 ("SMBIOS: Build aggregate smbios tables and entry point"). [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf The absence of this table is a breach of the specs and is detected by the FirmwareTestSuite (FWTS), but it doesn't cause any known problems for guest OSes. Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com> Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Add properties to disable high memory regionsGavin Shan1-2/+73
The 3 high memory regions are usually enabled by default, but they may be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2. This leads to waste in the PA space. Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to allow users selectively disable them if needed. After that, the high memory region for GICv3 or GICv4 redistributor can be disabled by user, the number of maximal supported CPUs needs to be calculated based on 'vms->highmem_redists'. The follow-up error message is also improved to indicate if the high memory region for GICv3 and GICv4 has been enabled or not. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20221029224307.138822-8-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Add 'compact-highmem' propertyGavin Shan1-0/+32
After the improvement to high memory region address assignment is applied, the memory layout can be changed, introducing possible migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region is disabled or enabled when the optimization is applied or not, with the following configuration. The configuration is only achievable by modifying the source code until more properties are added to allow users selectively disable those high memory regions. pa_bits = 40; vms->highmem_redists = false; vms->highmem_ecam = false; vms->highmem_mmio = true; # qemu-system-aarch64 -accel kvm -cpu host \ -machine virt-7.2,compact-highmem={on, off} \ -m 4G,maxmem=511G -monitor stdio Region compact-highmem=off compact-highmem=on ---------------------------------------------------------------- MEM [1GB 512GB] [1GB 512GB] HIGH_GIC_REDISTS2 [512GB 512GB+64MB] [disabled] HIGH_PCIE_ECAM [512GB+256MB 512GB+512MB] [disabled] HIGH_PCIE_MMIO [disabled] [512GB 1TB] In order to keep backwords compatibility, we need to disable the optimization on machine, which is virt-7.1 or ealier than it. It means the optimization is enabled by default from virt-7.2. Besides, 'compact-highmem' property is added so that the optimization can be explicitly enabled or disabled on all machine types by users. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-id: 20221029224307.138822-7-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Improve high memory region address assignmentGavin Shan1-5/+10
There are three high memory regions, which are VIRT_HIGH_REDIST2, VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses are floating on highest RAM address. However, they can be disabled in several cases. (1) One specific high memory region is likely to be disabled by code by toggling vms->highmem_{redists, ecam, mmio}. (2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is 'virt-2.12' or ealier than it. (3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded on 32-bits system. (4) One specific high memory region is disabled when it breaks the PA space limit. The current implementation of virt_set_{memmap, high_memmap}() isn't optimized because the high memory region's PA space is always reserved, regardless of whatever the actual state in the corresponding vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and 'vms->highest_gpa' are always increased for case (1), (2) and (3). It's unnecessary since the assigned PA space for the disabled high memory region won't be used afterwards. Improve the address assignment for those three high memory region by skipping the address assignment for one specific high memory region if it has been disabled in case (1), (2) and (3). The memory layout may be changed after the improvement is applied, which leads to potential migration breakage. So 'vms->highmem_compact' is added to control if the improvement should be applied. For now, 'vms->highmem_compact' is set to false, meaning that we don't have memory layout change until it becomes configurable through property 'compact-highmem' in next patch. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-id: 20221029224307.138822-6-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Introduce virt_get_high_memmap_enabled() helperGavin Shan1-13/+19
This introduces virt_get_high_memmap_enabled() helper, which returns the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will be used in the subsequent patches. No functional change intended. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-id: 20221029224307.138822-5-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()Gavin Shan1-6/+6
This introduces variable 'region_base' for the base address of the specific high memory region. It's the preparatory work to optimize high memory region address assignment. No functional change intended. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-id: 20221029224307.138822-4-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()Gavin Shan1-7/+8
This renames variable 'size' to 'region_size' in virt_set_high_memmap(). Its counterpart ('region_base') will be introduced in next patch. No functional change intended. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-id: 20221029224307.138822-3-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-15hw/arm/virt: Introduce virt_set_high_memmap() helperGavin Shan1-33/+41
This introduces virt_set_high_memmap() helper. The logic of high memory region address assignment is moved to the helper. The intention is to make the subsequent optimization for high memory region address assignment easier. No functional change intended. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> Message-id: 20221029224307.138822-2-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-14error: Move ERRP_GUARD() to the beginning of the functionMarkus Armbruster1-2/+1
include/qapi/error.h advises to put ERRP_GUARD() right at the beginning of the function, because only then can it guard the whole function. Clean up the few spots disregarding the advice. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221121085054.683122-4-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-12-14error: Drop some obviously superfluous error_propagate()Markus Armbruster1-9/+5
When error_propagate(errp, local_err) is the only reader of @local_err, we can just as well change its writers to write @errp directly, and drop the error_propagate() along with @local_err. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221121085054.683122-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-07Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi2-14/+20
into staging pci,pc,virtio: features, tests, fixes, cleanups lots of acpi rework first version of biosbits infrastructure ASID support in vhost-vdpa core_count2 support in smbios PCIe DOE emulation virtio vq reset HMAT support part of infrastructure for viommu support in vhost-vdpa VTD PASID support fixes, tests all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmNpXDkPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpD0AH/2G8ZPrgrxJC9y3uD5/5J6QRzO+TsDYbg5ut # uBf4rKSHHzcu6zdyAfsrhbAKKzyD4HrEGNXZrBjnKM1xCiB/SGBcDIWntwrca2+s # 5Dpbi4xvd4tg6tVD4b47XNDCcn2uUbeI0e2M5QIbtCmzdi/xKbFAfl5G8DQp431X # Kmz79G4CdKWyjVlM0HoYmdCw/4FxkdjD02tE/Uc5YMrePNaEg5Bw4hjCHbx1b6ur # 6gjeXAtncm9s4sO0l+sIdyiqlxiTry9FSr35WaQ0qPU+Og5zaf1EiWfdl8TRo4qU # EAATw5A4hyw11GfOGp7oOVkTGvcNB/H7aIxD7emdWZV8+BMRPKo= # =zTCn # -----END PGP SIGNATURE----- # gpg: Signature made Mon 07 Nov 2022 14:27:53 EST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (83 commits) checkpatch: better pattern for inline comments hw/virtio: introduce virtio_device_should_start tests/acpi: update tables for new core count test bios-tables-test: add test for number of cores > 255 tests/acpi: allow changes for core_count2 test bios-tables-test: teach test to use smbios 3.0 tables hw/smbios: add core_count2 to smbios table type 4 vhost-user: Support vhost_dev_start vhost: Change the sequence of device start intel-iommu: PASID support intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function intel-iommu: drop VTDBus intel-iommu: don't warn guest errors when getting rid2pasid entry vfio: move implement of vfio_get_xlat_addr() to memory.c tests: virt: Update expected *.acpihmatvirt tables tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators hw/arm/virt: Enable HMAT on arm virt machine tests: Add HMAT AArch64/virt empty table files tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT: tests: acpi: q35: add test for hmat nodes without initiators ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-07hw/arm/virt: Enable HMAT on arm virt machineXiang Chen2-0/+8
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"), HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20221027100037.251-7-hesham.almatary@huawei.com> Tested-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata AMiguel Luis1-9/+7
MADT has been updated with the GIC Structures from ACPI 6.0 Errata A and so MADT revision and GICC Structure must be updated also. Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix() API to compose MADT table") Signed-off-by: Miguel Luis <miguel.luis@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20221011181730.10885-4-miguel.luis@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07acpi: fadt: support revision 6.0 of the ACPI specificationMiguel Luis1-5/+5
Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI specification adding the field "Hypervisor Vendor Identity". This field's description states the following: "64-bit identifier of hypervisor vendor. All bytes in this field are considered part of the vendor identity. These identifiers are defined independently by the vendors themselves, usually following the name of the hypervisor product. Version information should NOT be included in this field - this shall simply denote the vendor's name or identifier. Version information can be communicated through a supplemental vendor-specific hypervisor API. Firmware implementers would place zero bytes into this field, denoting that no hypervisor is present in the actual firmware." Signed-off-by: Miguel Luis <miguel.luis@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20221011181730.10885-3-miguel.luis@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-04hw/arm/boot: Set SCR_EL3.HXEn when booting kernelPeter Maydell1-0/+3
When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For CPUs with FEAT_HCX support this includes: - SCR_EL3.HXEn (bit 38) must be initialised to 0b1. but we forgot to do this when implementing FEAT_HCX, which would mean that a guest trying to access the HCRX_EL2 register would crash. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
2022-11-04hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernelPeter Maydell1-0/+2
When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For SVE and SME this includes: - ZCR_EL3.LEN must be initialised to the same value for all CPUs the kernel is executed on. - SMCR_EL3.LEN must be initialised to the same value for all CPUs the kernel will execute on. Although we are technically compliant with this, the "same value" we currently use by default is the reset value of 0. This will end up forcing the guest kernel's SVE and SME vector length to be only the smallest supported length. Initialize the vector length fields to their maximum possible value, which is 0xf. If the implementation doesn't actually support that vector length then the effective vector length will be constrained down to the maximum supported value at point of use. This allows the guest to use all the vector lengths the emulated CPU supports (by programming the _EL2 and _EL1 versions of these registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221027140207.413084-2-peter.maydell@linaro.org
2022-10-27arm: re-randomize rng-seed on rebootJason A. Donenfeld1-0/+2
When the system reboots, the rng-seed that the FDT has should be re-randomized, so that the new boot gets a new seed. Since the FDT is in the ROM region at this point, we add a hook right after the ROM has been added, so that we have a pointer to that copy of the FDT. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-arm@nongnu.org Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-id: 20221025004327.568476-5-Jason@zx2c4.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-27reset: allow registering handlers that aren't called by snapshot loadingJason A. Donenfeld2-4/+4
Snapshot loading only expects to call deterministic handlers, not non-deterministic ones. So introduce a way of registering handlers that won't be called when reseting for snapshots. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-id: 20221025004327.568476-2-Jason@zx2c4.com [PMM: updated json doc comment with Markus' text; fixed checkpatch style nit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-10-27hw/arm/virt: Fix devicetree warnings about the virtio-iommu nodeJean-Philippe Brucker1-2/+3
The "PCI Bus Binding to: IEEE Std 1275-1994" defines the compatible string for a PCIe bus or endpoint as "pci<vendorid>,<deviceid>" or similar. Since the initial binding for PCI virtio-iommu didn't follow this rule, it was modified to accept both strings and ensure backward compatibility. Also, the unit-name for the node should be "device,function". Fix corresponding dt-validate and dtc warnings: pcie@10000000: virtio_iommu@16:compatible: ['virtio,pci-iommu'] does not contain items matching the given schema pcie@10000000: Unevaluated properties are not allowed (... 'virtio_iommu@16' were unexpected) From schema: linux/Documentation/devicetree/bindings/pci/host-generic-pci.yaml virtio_iommu@16: compatible: 'oneOf' conditional failed, one must be fixed: ['virtio,pci-iommu'] is too short 'pci1af4,1057' was expected From schema: dtschema/schemas/pci/pci-bus.yaml Warning (pci_device_reg): /pcie@10000000/virtio_iommu@16: PCI unit address format error, expected "2,0" Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-07-14 05:59:16 +0000