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2016-03-16machine: Use type_init() to register machine classesEduardo Habkost11-11/+11
Change all machine_init() users that simply call type_register*() to use type_init(). Cc: Evgeny Voevodin <e.voevodin@samsung.com> Cc: Maksim Kozlov <m.kozlov@samsung.com> Cc: Igor Mitsyanko <i.mitsyanko@gmail.com> Cc: Dmitry Solodkiy <d.solodkiy@samsung.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Rob Herring <robh@kernel.org> Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: "Hervé Poussineau" <hpoussin@reactos.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Acked-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-03-16bcm2835_dma: add emulation of Raspberry Pi DMA controllerGrégory ESTRADE1-0/+26
At present, all DMA transfers complete inline (so a looping descriptor queue will lock up the device). We also do not model pause/abort, arbitrarion/priority, or debug features. Signed-off-by: Grégory ESTRADE <gregory.estrade@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1457467526-8840-6-git-send-email-Andrew.Baumann@microsoft.com [AB: implement 2D mode, cleanup/refactoring for upstream submission] Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16bcm2835_property: implement framebuffer control/configuration propertiesGrégory ESTRADE2-12/+3
The property channel driver now interfaces with the framebuffer device to query and set framebuffer parameters. As a result of this, the "get ARM RAM size" query now correctly returns the video RAM base address (not total RAM size), and the ram-size property is no longer relevant here. Signed-off-by: Grégory ESTRADE <gregory.estrade@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1457467526-8840-5-git-send-email-Andrew.Baumann@microsoft.com [AB: cleanup/refactoring for upstream submission] Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16bcm2835_fb: add framebuffer device for Raspberry PiGrégory ESTRADE3-2/+43
The framebuffer occupies the upper portion of memory (64MiB by default), but it can only be controlled/configured via a system mailbox or property channel (to be added by a subsequent patch). Signed-off-by: Grégory ESTRADE <gregory.estrade@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1457467526-8840-4-git-send-email-Andrew.Baumann@microsoft.com [AB: added Windows (BGR) support and cleanup/refactoring for upstream submission] Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) blockAndrew Baumann1-0/+32
At present only the core UART functions (data path for tx/rx) are implemented, which is enough for UEFI to boot. The following features/registers are unimplemented: * Line/modem control * Scratch register * Extra control * Baudrate * SPI interfaces Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1457467526-8840-3-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16bcm2835_peripherals: enable sdhci pending-insert quirk for raspberry piAndrew Baumann1-0/+7
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1457467526-8840-2-git-send-email-Andrew.Baumann@microsoft.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16hw/arm: Add palmetto-bmc machineAndrew Jeffery2-1/+66
The new machine is a thin layer over the AST2400 ARM926-based SoC[1]. Between the minimal machine and the current SoC implementation there is enough functionality to boot an aspeed_defconfig Linux kernel to userspace. Nothing yet is specific to the Palmetto's BMC (other than using an AST2400 SoC), but creating specific machine types is preferable to a generic machine that doesn't match any particular hardware. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-5-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16hw/arm: Add ASPEED AST2400 SoC modelAndrew Jeffery2-0/+138
While the ASPEED AST2400 SoC[1] has a broad range of capabilities this implementation is minimal, comprising an ARM926 processor, ASPEED VIC and timer devices, and a 8250 UART. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-4-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16i.MX: Add missing descriptions in devices.Jean-Christophe Dubois2-0/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: f1f565eb9dffdeb582feb1b15ba9e8b0afcf5468.1456868959.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16arm: virt: Move machine class init code to the abstract machine typeWei Huang1-14/+20
This patch moves the common class initialization code from "virt-2.6" to the new abstract class. An empty property is added to "virt-2.6" machine. In the meanwhile, related funtions are renamed to "virt_2_6_*" for consistency. Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1457717778-17727-3-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16arm: virt: Add an abstract ARM virt machine typeWei Huang1-5/+18
In preparation for future ARM virt machine types, this patch creates an abstract type for all ARM machines. The current machine type in QEMU (i.e. "virt") is renamed to "virt-2.6", whose naming scheme is similar to other architectures. For the purpose of backward compatibility, "virt" is converted to an alias, pointing to "virt-2.6". With this patch, "qemu -M ?" lists the following virtual machine types along with others: virt QEMU 2.6 ARM Virtual Machine (alias of virt-2.6) virt-2.6 QEMU 2.6 ARM Virtual Machine Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1457717778-17727-2-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-10vfio: Generalize region supportAlex Williamson1-2/+2
Both platform and PCI vfio drivers create a "slow", I/O memory region with one or more mmap memory regions overlayed when supported by the device. Generalize this to a set of common helpers in the core that pulls the region info from vfio, fills the region data, configures slow mapping, and adds helpers for comleting the mmap, enable/disable, and teardown. This can be immediately used by the PCI MSI-X code, which needs to mmap around the MSI-X vector table. This also changes VFIORegion.mem to be dynamically allocated because otherwise we don't know how the caller has allocated VFIORegion and therefore don't know whether to unreference it to destroy the MemoryRegion or not. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-03-08acpi: arm: add fw_cfg device node to dsdtGabriel L. Somlo1-0/+15
Add a fw_cfg device node to the ACPI DSDT. This is mostly informational, as the authoritative fw_cfg MMIO region(s) are listed in the Device Tree. However, since we are building ACPI tables, we might as well be thorough while at it... Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Marc Marí <markmb@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1455906029-25565-5-git-send-email-somlo@cmu.edu Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-03-04arm: boot: Support big-endian elfsPeter Crosthwaite1-10/+83
Support ARM big-endian ELF files in system-mode emulation. When loading an elf, determine the endianness mode expected by the elf, and set the relevant CPU state accordingly. With this, big-endian modes are now fully supported via system-mode LE, so there is no need to restrict the elf loading to the TARGET endianness so the ifdeffery on TARGET_WORDS_BIGENDIAN goes away. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fix typo in comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: Add data swap option to load-elfPeter Crosthwaite2-2/+2
Some CPUs are of an opposite data-endianness to other components in the system. Sometimes elfs have the data sections layed out with this CPU data-endianness accounting for when loaded via the CPU, so byte swaps (relative to other system components) will occur. The leading example, is ARM's BE32 mode, which is is basically LE with address manipulation on half-word and byte accesses to access the hw/byte reversed address. This means that word data is invariant across LE and BE32. This also means that instructions are still LE. The expectation is that the elf will be loaded via the CPU in this endianness scheme, which means the data in the elf is reversed at compile time. As QEMU loads via the system memory directly, rather than the CPU, we need a mechanism to reverse elf data endianness to implement this possibility. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is providedPeter Maydell1-7/+25
If the user passes us an EL3 boot rom, then it is going to want to implement the PSCI interface itself. In this case, disable QEMU's internal PSCI implementation so it does not get in the way, and instead start all CPUs in an SMP configuration at once (the boot rom will catch them all and pen up the secondaries until needed). The boot rom code is also responsible for editing the device tree to include any necessary information about its own PSCI implementation before eventually passing it to a NonSecure guest. (This "start all CPUs at once" approach is what both ARM Trusted Firmware and UEFI expect, since it is what the ARM Foundation Model does; the other approach would be to provide some emulated hardware for "start the secondaries" but this is simplest.) This is a compatibility break, but I don't believe that anybody was using a secure boot ROM with an SMP configuration. Such a setup would be somewhat broken since there was nothing preventing nonsecure guest code from calling the QEMU PSCI function to start up a secondary core in a way that completely bypassed the secure world. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-id: 1456853976-7592-1-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Make first flash device Secure-only if booting securePeter Maydell1-14/+49
If the virt board is started with the 'secure' property set to request a Secure setup, then make the first flash device be visible only to the Secure world. This is a breaking change, but I don't expect it to be noticed by anybody, because running TZ-aware guests isn't common and those guests are generally going to be booting from the flash and implicitly expecting their Non-secure guests to not touch it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-5-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Load bios image to MemoryRegion, not physaddrPeter Maydell1-19/+20
If we're loading a BIOS image into the first flash device, load it into the flash's memory region specifically, not into the physical address where the flash resides. This will make a difference when the flash might be in the Secure address space rather than the Nonsecure one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-4-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell1-0/+23
If we're booting in Secure mode, provide a secure-only RAM (just 16MB) so that secure firmware has somewhere to run from that won't be accessible to the Non-secure guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-2-git-send-email-peter.maydell@linaro.org
2016-03-04virt: Lift the maximum RAM limit from 30GB to 255GBPeter Maydell1-2/+19
The virt board restricts guests to only 30GB of RAM. This is a hangover from the vexpress-a15 board, and there's no inherent reason for it. 30GB is smaller than you might reasonably want to provision a VM for on a beefy server machine. Raise the limit to 255GB. We choose 255GB because the available space we currently have below the 1TB boundary is up to the 512GB mark, but we don't want to paint ourselves into a corner by assigning it all to RAM. So we make half of it available for RAM, with the 256GB..512GB range available for future non-RAM expansion purposes. If we need to provide more RAM to VMs in the future then we need to: * allocate a second bank of RAM starting at 2TB and working up * fix the DT and ACPI table generation code in QEMU to correctly report two split lumps of RAM to the guest * fix KVM in the host kernel to allow guests with >40 bit address spaces The last of these is obviously the trickiest, but it seems reasonable to assume that anybody configuring a VM with a quarter of a terabyte of RAM will be doing it on a host with more than a terabyte of physical address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1456402182-11651-1-git-send-email-peter.maydell@linaro.org
2016-02-26raspi: fix SD card with recent sdhci changesAndrew Baumann3-0/+30
Recent changes to sdhci broke SD on raspi. This change mirrors the logic to create the SD card device at the board level. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456351128-5560-1-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-23bios-linker-loader: document+validate inputMichael S. Tsirkin1-1/+2
While guest/host ABI is documented in hw/acpi/bios-linker-loader.c, the API was left undocumented. This adds documentation for all API functions. Additionally, input is validated to make sure all pointers fall within range of provided files. To allow this validation for checksum commands, bios_linker_loader_add_checksum is changed to accept GArray * in place of void *. Reported-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-02-19hw/arm/sysbus-fdt: remove qemu_fdt_setprop returned value checkEric Auger1-14/+5
qemu_fdt_setprop asserts in case of error hence no need to check the returned value. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-02-19hw/arm/sysbus-fdt: enable amd-xgbe dynamic instantiationEric Auger1-6/+188
This patch allows the instantiation of the vfio-amd-xgbe device from the QEMU command line (-device vfio-amd-xgbe,host="<device>"). The guest is exposed with a device tree node that combines the description of both XGBE and PHY (representation supported from 4.2 onwards kernel): Documentation/devicetree/bindings/net/amd-xgbe.txt. There are 5 register regions, 6 interrupts including 4 optional edge-sensitive per-channel interrupts. Some property values are inherited from host device tree. Host device tree must feature a combined XGBE/PHY representation (>= 4.2 host kernel). 2 clock nodes (dma and ptp) also are created. It is checked those clocks are fixed on host side. AMD XGBE node creation function has a dependency on vfio Linux header and more generally node creation function for VFIO platform devices only make sense with CONFIG_LINUX so let's protect this code with #ifdef CONFIG_LINUX. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-02-19hw/arm/sysbus-fdt: helpers for clock node generationEric Auger1-0/+120
Some passthrough'ed devices depend on clock nodes. Those need to be generated in the guest device tree. This patch introduces some helpers to build a clock node from information retrieved in the host device tree. - copy_properties_from_host copies properties from a host device tree node to a guest device tree node - fdt_build_clock_node builds a guest clock node and checks the host fellow clock is a fixed one. fdt_build_clock_node will become static as soon as it gets used. A dummy pre-declaration is needed for compilation of this patch. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-02-19device_tree: qemu_fdt_getprop_cell converted to use the error APIEric Auger2-4/+8
This patch aligns the prototype with qemu_fdt_getprop. The caller can choose whether the function self-asserts on error (passing &error_fatal as Error ** argument, corresponding to the legacy behavior), or behaves differently such as simply output a message. In this later case the caller can use the new lenp parameter to interpret the error if any. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-02-18sdhci_sysbus: Create SD card device in users, not the device itselfPeter Maydell3-1/+45
Move the creation of the SD card device from the sdhci_sysbus device itself into the boards that create these devices. This allows us to remove the cannot_instantiate_with_device_add notation because we no longer call drive_get_next in the device model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1455646193-13238-7-git-send-email-peter.maydell@linaro.org
2016-02-16all: Clean up includesPeter Maydell3-0/+3
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-02-11bcm2835_property: implement "get board revision" queryStephen Warren3-0/+6
Return a valid value from the BCM2835 property mailbox query "get board revision". This query is used by U-Boot. Implementing it fixes the first obvious difference between qemu and real HW. The value returned is currently hard-coded to match the RPi2 I own. Other values are legal, e.g. different board manufacturer field values are likely to exist in the wild. Cc: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1454993910-24077-1-git-send-email-swarren@wwwdotorg.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-11hw/arm/virt: fix max-cpus checkAndrew Jones1-5/+5
mach-virt doesn't yet support hotplug, but command lines specifying -smp <num>,maxcpus=<bigger-num> don't fail. Of course specifying bigger-num as something bigger than the machine supports, e.g. > 8 on a gicv2 machine, should fail though. This fix also makes mach- virt's max-cpus check truly consistent with the one in vl.c:main, as the one there was already correctly checking max-cpus instead of smp-cpus. Reported-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1454511578-24863-1-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-08Use error_fatal to simplify obvious fatal errors (again)Markus Armbruster4-24/+4
Done with the Coccinelle semantic patch from commit 007b065, plus manual clean up of dead variables. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <1452783732-6581-1-git-send-email-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-02-08Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell1-7/+7
pc and misc cleanups and fixes, virtio optimizations Included here: Refactoring and bugfix patches in PC/ACPI. New commands for ipmi. Virtio optimizations. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sat 06 Feb 2016 18:44:26 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: (45 commits) net: set endianness on all backend devices fix MSI injection on Xen intel_iommu: large page support dimm: Correct type of MemoryHotplugState->base pc: set the OEM fields in the RSDT and the FADT from the SLIC acpi: add function to extract oem_id and oem_table_id from the user's SLIC acpi: expose oem_id and oem_table_id in build_rsdt() acpi: take oem_id in build_header(), optionally pc: Eliminate PcGuestInfo struct pc: Move APIC and NUMA data from PcGuestInfo to PCMachineState pc: Move PcGuestInfo.fw_cfg to PCMachineState pc: Remove PcGuestInfo.isapc_ram_fw field pc: Remove RAM size fields from PcGuestInfo pc: Remove compat fields from PcGuestInfo acpi: Don't save PcGuestInfo on AcpiBuildState acpi: Remove guest_info parameters from functions pc: Simplify xen_load_linux() signature pc: Simplify pc_memory_init() signature pc: Eliminate struct PcGuestInfoState pc: Move PcGuestInfo declaration to top of file ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-06acpi: expose oem_id and oem_table_id in build_rsdt()Laszlo Ersek1-1/+1
Since build_rsdt() is implemented as common utility code (in "hw/acpi/aml-build.c"), it should expose -- and forward -- the oem_id and oem_table_id parameters between board code and the generic build_header() function. Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:ACPI/SMBIOS) Cc: Igor Mammedov <imammedo@redhat.com> (supporter:ACPI/SMBIOS) Cc: Shannon Zhao <zhaoshenglong@huawei.com> (maintainer:ARM ACPI Subsystem) Cc: Paolo Bonzini <pbonzini@redhat.com> (maintainer:X86) Cc: Richard W.M. Jones <rjones@redhat.com> Cc: Aleksei Kovura <alex3kov@zoho.com> Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Steven Newbury <steve@snewbury.org.uk> RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1248758 LP: https://bugs.launchpad.net/qemu/+bug/1533848 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
2016-02-06acpi: take oem_id in build_header(), optionallyLaszlo Ersek1-6/+6
This patch is the continuation of commit 8870ca0e94f2 ("acpi: support specified oem table id for build_header"). It will allow us to control the OEM ID field too in the SDT header. Cc: "Michael S. Tsirkin" <mst@redhat.com> (supporter:ACPI/SMBIOS) Cc: Igor Mammedov <imammedo@redhat.com> (supporter:ACPI/SMBIOS) Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com> (maintainer:NVDIMM) Cc: Shannon Zhao <zhaoshenglong@huawei.com> (maintainer:ARM ACPI Subsystem) Cc: Paolo Bonzini <pbonzini@redhat.com> (maintainer:X86) Cc: Richard W.M. Jones <rjones@redhat.com> Cc: Aleksei Kovura <alex3kov@zoho.com> Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Steven Newbury <steve@snewbury.org.uk> RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=1248758 LP: https://bugs.launchpad.net/qemu/+bug/1533848 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
2016-02-03raspi: add raspberry pi 2 machineAndrew Baumann2-1/+153
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03arm/boot: move highbank secure board setup code to common routineAndrew Baumann2-35/+53
The new version is slightly different, to support Rasbperry Pi (in particular, Pi1's arm11 core which doesn't support v7 instructions such as MOVW). Tested-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03bcm2836: add bcm2836 SoC deviceAndrew Baumann2-1/+166
This is the SoC for Raspberry Pi 2. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03bcm2835_peripherals: add rollup device for bcm2835 peripheralsAndrew Baumann2-0/+205
This device maintains all the non-CPU peripherals on bcm2835 (Pi1) which are also present on bcm2836 (Pi2). It also implements the private address spaces used for DMA and mailboxes. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03arm: virt-acpi: each MADT.GICC entry as enabled unconditionallyIgor Mammedov1-23/+3
in current impl. condition build_madt() { ... if (test_bit(i, cpuinfo->found_cpus)) is always true since loop handles only present CPUs in range [0..smp_cpus). But to fill usless cpuinfo->found_cpus we do unnecessary scan over QOM tree to find the same CPUs. So mark GICC as present always and drop not needed code that fills cpuinfo->found_cpus. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1454323689-248759-1-git-send-email-imammedo@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux bootsEdgar E. Iglesias1-0/+2
When booting Linux on AArch64 enabled cores, setup EL1 and EL2 to use AArch64. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03virt-acpi-build: add always-on property for timerAndrew Jones1-1/+1
This patch is the ACPI equivalent of "hw/arm/virt: Add always-on property to the virt board timer". The timer is always on, and thus setting this informs Linux that it may switch off the periodic timer. Switching off the periodic timer substantially reduces the number of interrupts the host needs to inject. Testing note: AArch64 guests (the only ones currently booting with ACPI) do not actually need this patch to determine it can turn the periodic timer off. I therefore used a hacked guest kernel to ensure this patch works as the equivalent DT patch does. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1453380893-26174-1-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21hw/arm/virt: Add always-on property to the virt board timerChristoffer Dall1-0/+1
The virt board has an arch timer, which is always on. Emit the "always-on" property to indicate to Linux that it can switch off the periodic timer and reduces the amount of interrupts injected into a guest. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1453204158-11412-1-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21hw/arm/virt: add secure memory region and UARTPeter Maydell1-7/+48
Add a secure memory region to the virt board, which is the same as the nonsecure memory region except that it also has a secure-only UART in it. This is only created if the board is started with the '-machine secure=on' property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21hw/arm/virt: Wire up memory region to CPUs explicitlyPeter Maydell1-0/+3
Wire up the system memory region to the CPUs explicitly by setting the QOM property. This doesn't change anything over letting it default, but will be needed for adding a secure memory region later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21xlnx-ep108: Connect the SPI FlashAlistair Francis1-0/+16
Connect the sst25wf080 SPI flash to the EP108 board. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21xlnx-zynqmp: Connect the SPI devicesAlistair Francis1-0/+31
Connect the Xilinx SPI devices to the ZynqMP model. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [ PC changes * Use QOM alias for bus connectivity on SoC level ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [PMM: free the g_strdup_printf() string when finished with it] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21ssi: Move ssi.h into a separate directoryAlistair Francis7-7/+7
Move the ssi.h include file into the ssi directory. While touching the code also fix the typdef lines as checkpatch complains. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-18hw/arm: Clean up includesPeter Maydell42-1/+42
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1449505425-32022-4-git-send-email-peter.maydell@linaro.org
2016-01-15ARM: virt: Don't generate RTC ACPI device when using UEFIShannon Zhao1-19/+5
When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. While UEFI can use libfdt to disable the RTC device node in the DTB that it passes to the OS, it cannot modify AML. Therefore, we won't generate the RTC ACPI device at all when using UEFI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1452867091-4023-1-git-send-email-shannon.zhao@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-15xlnx-zynqmp: Add support for high DDR memory regionsAlistair Francis2-19/+58
The Xilinx ZynqMP SoC and EP108 board supports three memory regions: - A 2GB region starting at 0 - A 32GB region starting at 32GB - A 256GB region starting at 768GB This patch adds support for the first two memory regions, which is automatically created based on the size specified by the QEMU memory command line argument. On hardware the physical memory region is one continuous region, it is then mapped into the three different regions by the DDRC. As we don't model the DDRC this is done at startup by QEMU. The board creates the memory region and then passes that memory region to the SoC. The SoC then maps the memory regions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: a1e47db941d65733724a300fcd98b74fbeeaaf22.1452637205.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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