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2014-05-13hw/arm/stellaris: Correct handling of GPTM TAR registerPeter Maydell1-3/+10
We don't implement very much of the GPTM TAR register, and what we do is wrong. The "are we in RT mode?" field is in s->config, not s->control. Correct this, use LOG_UNIMP rather than hw_error() for the cases we don't support, and avoid an unlabelled fallthrough that makes Coverity complain. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-05-13hw/arm/omap1: Avoid unintended sign extension writing omap_rtc YEARS_REGPeter Maydell1-2/+2
When writing to the YEARS_REG register, if the year value is 99 then the multiplication by 31536000 will overflow into the sign bit of a 32 bit value and then be erroneously sign-extended if time_t is 64 bits. Add a cast to avoid this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-05-13savevm: Remove all the unneeded version_minimum_id_old (arm)Juan Quintela9-49/+15
After commit 767adce2d, they are redundant. This way we don't assign them except when needed. Once there, there were lots of cases where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (apart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed minor conflict, corrected commit message typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-05pxa2xx: avoid buffer overrun on incoming migrationMichael S. Tsirkin1-2/+6
CVE-2013-4533 s->rx_level is read from the wire and used to determine how many bytes to subsequently read into s->rx_fifo[]. If s->rx_level exceeds the length of s->rx_fifo[] the buffer can be overrun with arbitrary data from the wire. Fix this by validating rx_level against the size of s->rx_fifo. Cc: Don Koch <dkoch@verizon.com> Reported-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Don Koch <dkoch@verizon.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2014-05-01hw/arm/virt: Add support for Cortex-A57Peter Maydell1-0/+5
Support the Cortex-A57 in the virt machine model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-4-git-send-email-peter.maydell@linaro.org
2014-05-01hw/arm/virt: Put GIC register banks on 64K boundariesPeter Maydell1-3/+3
For an AArch64 CPU which supports 64K pages, having the GIC register banks at 4K offsets is potentially awkward. Move them out to being at 64K offsets. (This is harmless for AArch32 CPUs and for AArch64 CPUs with 4K pages, so it is simpler to use the same offsets everywhere than to try to use 64K offsets only for AArch64 host CPUs.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-3-git-send-email-peter.maydell@linaro.org
2014-05-01hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_privPeter Maydell1-29/+53
Rather than having the virt machine model create an a15mpcore_priv device regardless of the actual CPU type in order to instantiate the GIC, move to having the machine model create the GIC directly. This corresponds to a system which uses a standalone GIC (eg the GIC-400) rather than the one built in to the CPU core. The primary motivation for this is to support the Cortex-A57, which for a KVM configuration will use a GICv2, which is not built into the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-2-git-send-email-peter.maydell@linaro.org
2014-04-17allwinner-a10-pit: implement prescaler and source selectionBeniamino Galvani1-0/+13
This implements the prescaler and source fields of the timer control register. The source for each timer can be selected among 4 clock inputs whose frequencies are set through model properties. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-6-git-send-email-b.galvani@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-04hw/arm/vexpress, hw/arm/highbank: Don't insist that CPU has reset-cbar propertyPeter Maydell2-11/+10
For the machine models which can have a Cortex-A15 CPU (vexpress-a15 and midway), silently continue if the CPU object has no reset-cbar property rather than failing. This allows these boards to be used under KVM with the "-cpu host" option, since the 'host' CPU object has no reset-cbar property. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Rob Herring <rob.herring@linaro.org>
2014-04-04hw/arm/highbank: Don't segfault on unknown CPU namesPeter Maydell1-0/+5
If the user passes an unknown CPU name via the '-cpu' option, exit with an error message rather than segfaulting. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Rob Herring <rob.herring@linaro.org>
2014-03-27hw/arm: Stop specifying integratorcp as the default boardPeter Maydell1-1/+0
Currently for both qemu-system-arm and qemu-system-aarch64 the default board model if the user doesn't specify one is the 'integratorcp'. This is a totally arbitrary historical accident since it was the first board to be modelled. That board is now just one target among many for us, and is a very poor choice of default: * it's an ancient board that is now only found in the junkpiles of longtime ARM/Linux hackers, if at all * it's an ARMv5 CPU, when most distros are now assuming ARMv7 * it's pretty much unmaintained in QEMU * it doesn't even have versatilepb's advantage of supporting PCI Making it or any other board the default serves only to confuse people new to ARM who expect something more like the x86 monoculture. Remove the is_default marker from integratorcp, and don't set it for any other board, to give users a nudge that they need to think about which board they want a QEMU model of. (QEMU will produce the admittedly slightly cryptic error "No machine found.") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-24target-arm: Load ELF images with the correct machine type for CPUPeter Maydell1-1/+4
When trying to load an ELF file specified via -kernel, we need to pass load_elf() the ELF machine type corresponding to the CPU we're booting with, not the one corresponding to the softmmu binary we happen to be running. (The two are different in the case of loading a 32-bit ARM ELF file into a 32 bit CPU being emulated by qemu-system aarch64.) This was causing us to incorrectly fail to load ELF images in this situation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1395427476-25546-1-git-send-email-peter.maydell@linaro.org
2014-03-17virt: Set reset-cbar on CPUsPeter Maydell1-0/+6
Set the reset-cbar property on CPUs used by the virt board, if they have it. This isn't necessary for correct functioning under Linux (since the A9 isn't a valid CPU for the virt board), but it is the correct behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-5-git-send-email-peter.maydell@linaro.org
2014-03-17exynos4210: Set reset-cbar property of Cortex-A9 CPUsPeter Maydell1-3/+13
Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9 CPUs, so that Linux doesn't misrecognize them as a broken uniprocessor SoC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-4-git-send-email-peter.maydell@linaro.org
2014-03-17realview-pbx-a9: Set reset-cbar property for CPUsPeter Maydell1-10/+29
If the CPU is a Cortex-A9 then we should set its reset-cbar property so that the guest can read the correct PERIPHBASE/CBAR register value; newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) will otherwise assume the CPU is a buggy single core A9 SoC. The realview-pbx-a9 is the only one of the cluster of boards in realview.c which works with the Cortex-A9 (ie which gets an a9mpcore_priv device); make sure it also has reset-cbar set correctly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-3-git-send-email-peter.maydell@linaro.org
2014-03-17vexpress: Set reset-cbar property for CPUsPeter Maydell1-62/+61
Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12) now assume that if the CPU is a Cortex-A9 and the reset value of the PERIPHBASE/CBAR register is zero then the CPU is a specific buggy single core A9 SoC, and will not try to start other cores. Since we now have a CPU property for the reset value of the CBAR, we can just fix the vexpress board model to correctly set CBAR so SMP works again. To avoid duplicate boilerplate code in both the A9 and A15 daughterboard init functions, we split out the CPU and private memory region init to its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1394462692-8871-2-git-send-email-peter.maydell@linaro.org
2014-03-12ssi: Convert legacy SSI_SLAVE -> DEVICE castsPeter Crosthwaite1-6/+7
Convert legacy ->qdev style casts from TYPE_SSI_SLAVE to TYPE_DEVICE. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Introduce local DeviceState variable for transition to QOM realize] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-10hw/arm/musicpal: Avoid shifting left into sign bitPeter Maydell1-2/+2
Add missing 'U' suffixes to avoid shifting left into sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-5-git-send-email-peter.maydell@linaro.org
2014-03-10hw/arm/omap1.c: Avoid shifting left into sign bitPeter Maydell1-10/+14
Add missing 'U' suffix to avoid shifting left into sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-3-git-send-email-peter.maydell@linaro.org
2014-03-10pxa2xx: Don't shift into sign bitPeter Maydell3-6/+6
Add missing 'U' suffixes to avoid potentially shifting into the sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-2-git-send-email-peter.maydell@linaro.org
2014-03-05console: add head to index to qemu consoles.Gerd Hoffmann1-1/+1
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell1-2/+2
To avoid complication in code that otherwise would not need to care about whether EL1 is AArch32 or AArch64, we should store the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF in AArch64) in one place consistently regardless of EL1's mode. Since AArch64 has an extra enable bit (D for debug exceptions) which isn't visible in AArch32, this means we need to keep the enables in env->pstate. (This is also consistent with the general approach we're taking that we handle 32 bit CPUs as being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 TTBR*Peter Maydell1-1/+1
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits to handle LPAE, but implemented as two separate uint32_t fields. Combine them into a single uint64_t which can be used for all purposes. Since this requires touching every use, take the opportunity to rename the field to the architectural name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registersPeter Maydell1-4/+2
The ethernet device in the musicpal only has two tx queues, but we modelled it with four CTDP registers, presumably a cut and paste from the rx queue registers. Since the tx_queue[] array is only 2 entries long this allowed a guest to overrun this buffer. Remove the nonexistent registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392737293-10073-1-git-send-email-peter.maydell@linaro.org Acked-by: Jan Kiszka <jan.kiszka@web.de> Cc: qemu-stable@nongnu.org
2014-02-21Merge remote-tracking branch ↵Peter Maydell2-30/+17
'remotes/pmaydell/tags/pull-target-arm-20140220' into staging target-arm queue: * Fix a bug causing an assertion in the NVIC on ARMv7M models * More A64 Neon instructions * Refactor cpreg API to separate out access check functions, as groundwork for AArch64 system mode * Fix bug in linux-user A64 store-exclusive of XZR # gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits) linux-user: AArch64: Fix exclusive store of the zero register target-arm: A64: Implement unprivileged load/store target-arm: A64: Implement narrowing three-reg-diff operations target-arm: A64: Implement the wide 3-reg-different operations target-arm: A64: Add most remaining three-reg-diff widening ops target-arm: A64: Add opcode comments to disas_simd_three_reg_diff target-arm: A64: Implement store-exclusive for system mode target-arm: Fix incorrect type for value argument to write_raw_cp_reg target-arm: Remove failure status return from read/write_raw_cp_reg target-arm: Remove unnecessary code now read/write fns can't fail target-arm: Drop success/fail return from cpreg read and write functions target-arm: Convert miscellaneous reginfo structs to accessfn target-arm: Convert generic timer reginfo to accessfn target-arm: Convert performance monitor reginfo to accessfn target-arm: Split cpreg access checks out from read/write functions target-arm: Stop underdecoding ARM946 PRBS registers target-arm: Log bad system register accesses with LOG_UNIMP target-arm: Remove unused ARMCPUState sr substruct target-arm: Restrict check_ap() use of S and R bits to v6 and earlier target-arm: Define names for SCTLR bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell2-30/+17
All cpreg read and write functions now return 0, so we can clean up their prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to This is a fairly mechanical change which makes only the bare minimum set of changes to the callers of read and write functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-14z2: QOM'ify AER915Andreas Färber1-7/+13
Replace usages of FROM_I2C_SLAVE() with QOM cast macro. Rename the parent field. Reuse the type constant in z2_init(). Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [AF: Use TYPE_AER915 in z2_init() too] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-14tosa: QOM'ify DACAndreas Färber1-5/+11
Replace usages of FROM_I2C_SLAVE() with QOM cast macro. Rename parent field. Use type constant in tosa_tg_init(). Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-14pxa2xx: QOM'ify I2C slaveAndreas Färber1-13/+25
Replace usages of FROM_I2C_SLAVE() and direct parent field accesses with QOM cast macro. Rename parent field to assure we caught all. Reuse type constant in pxa2xx_i2c_init(). Add some missing braces while at it. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-14i2c: Rename i2c_bus to I2CBusAndreas Färber10-18/+18
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-11exec: Make stl_phys_notdirty input an AddressSpaceEdgar E. Iglesias2-5/+6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-08hw/arm/allwinner-a10: initialize EMACBeniamino Galvani2-2/+25
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-04vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-typePeter Maydell1-1/+1
The VMSTATE_STRUCT_POINTER macros are a bit odd in that they must be passed an argument "FooType *" rather than just taking the FooType. They're only used in one place, so it's easy to tidy this up. This also lets us use the macro to replace the hand-rolled VMSTATE_PTIMER. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Juan Quintela <quintela@redhat.com>
2014-01-31ZYNQ: Implement board MIDR control for ZynqAlistair Francis1-0/+7
This patch uses the fact that the midr variable is now a property This patch sets the midr variable to the boards custom midr Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-31hw/arm/boot: Don't set up ATAGS for autogenerated dtb bootingPeter Maydell1-2/+7
The code which decides whether to set up the ATAGS data structure on reset was using the wrong conditional, which meant we were creating an ATAGS structure when doing a device-tree boot if the dtb was autogenerated by the board. This is harmless, but unnecessary, so bring it in to line with user-provided-dtb boots. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1388326833-656-1-git-send-email-peter.maydell@linaro.org
2014-01-09Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into ↵Anthony Liguori1-1/+0
staging QOM infrastructure fixes and device conversions * QOM interface fixes and unit test * Device no_user sanitization and documentation * Device error reporting improvement * Conversion of APIC, ICC, IOAPIC to QOM realization model # gpg: Signature made Tue 24 Dec 2013 09:04:05 AM PST using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F * afaerber/tags/qom-devices-for-anthony: (24 commits) qdev-monitor: Improve error message for -device nonexistant ioapic: QOM'ify ioapic ioapic: Cleanup for QOM'ification icc_bus: QOM'ify ICC apic: QOM'ify APIC apic: Cleanup for QOM'ification qdev: Drop misleading qbus_free() function qom: Detect bad reentrance during object_class_foreach() tests: Test QOM interface casting qom: Do not register interface "types" in the type table and fix names qom: Split out object and class caches qdev: Document that pointer properties kill device_add hw: cannot_instantiate_with_device_add_yet due to pointer props qdev-monitor: Avoid device_add crashing on non-device driver name qdev: Do not let the user try to device_add when it cannot work isa: Clean up use of cannot_instantiate_with_device_add_yet vt82c686: Clean up use of cannot_instantiate_with_device_add_yet piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet ich9: Document why cannot_instantiate_with_device_add_yet pci-host: Consistently set cannot_instantiate_with_device_add_yet ...
2014-01-09Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori3-8/+16
* mjt/trivial-patches: acpi unit-test: Remove temporary disk after test mainstone: Fix duplicate array values for key 'space' pxa27x: Add 'const' attribute to keyboard maps pxa27x: Reduce size of keyboard matrix mapping doc: Mention chardev:id in available devices for -serial configure: Python tests must be done before help message configure: Rewrite code for help message fix -boot strict regressed in commit 6ef4716 vl: make boot_strict variable static (not used outside vl.c) x86: only allow real mode to access 32bit without LMA linux-user: Use macro TARGET_NSIG_WORDS where possible exynos4210: Use macro ARRAY_SIZE where possible ui/cocoa: Use macro ARRAY_SIZE where possible misc: Use macro ARRAY_SIZE where possible openrisc: Fix spelling in comment (transaltion -> translation) hw/arm/highbank: Simplify code (memory region in device state) Message-id: 1388182050-10270-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-08arm/xilinx_zynq: Always instantiate the GEMsPeter Crosthwaite1-11/+6
Don't conditionalise GEM instantiation on networking attachments. The device should always be present even if not attached to a network. This allows for probing of the device by expectant guests (such as OS's). This is needed because sysbus (or AXI in Xilinx's real hw case) is not self identifying so the guest has no dynamic way of detecting device absence. Also allows for testing of the GEM in loopback mode with -net none. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 55649779a68ee3ff54b24c339b6fdbdccd1f0ed7.1388800598.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-01mainstone: Fix duplicate array values for key 'space'Stefan Weil1-2/+11
cgcc reported a duplicate initialisation. Mainstone includes a matrix keyboard where two different positions map to 'space'. QEMU uses the reversed mapping and does not map 'space' to two different matrix positions. Some other keys are either missing or might be mapped wrongly (cf. Linux kernel code). Don't fix these until someone can test them with real hardware, but add TODO comments. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-01-01pxa27x: Add 'const' attribute to keyboard mapsStefan Weil2-2/+2
The mapping is a hardware feature, so it is relatively constant. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23hw/arm/highbank: Simplify code (memory region in device state)Stefan Weil1-4/+3
The memory region can be included by value instead of by reference in the device state. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23sysbus: Set cannot_instantiate_with_device_add_yetMarkus Armbruster1-1/+0
device_add plugs devices into suitable bus. For "real" buses, that actually connects the device. For sysbus, the connections need to be made separately, and device_add can't do that. The device would be left unconnected, and could not possibly work. Quite a few, but not all sysbus devices already set cannot_instantiate_with_device_add_yet in their class init function. Set it in their abstract base's class init function sysbus_device_class_init(), and remove the now redundant assignments from device class init functions. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23qdev: Replace no_user by cannot_instantiate_with_device_add_yetMarkus Armbruster1-1/+1
In an ideal world, machines can be built by wiring devices together with configuration, not code. Unfortunately, that's not the world we live in right now. We still have quite a few devices that need to be wired up by code. If you try to device_add such a device, it'll fail in sometimes mysterious ways. If you're lucky, you get an unmysterious immediate crash. To protect users from such badness, DeviceClass member no_user used to make device models unavailable with -device / device_add, but that regressed in commit 18b6dad. The device model is still omitted from help, but is available anyway. Attempts to fix the regression have been rejected with the argument that the purpose of no_user isn't clear, and it's prone to misuse. This commit clarifies no_user's purpose. Anthony suggested to rename it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which I shorten somewhat to keep checkpatch happy. While there, make it bool. Every use of cannot_instantiate_with_device_add_yet gets a FIXME comment asking for rationale. The next few commits will clean them all up, either by providing a rationale, or by getting rid of the use. With that done, the regression fix is hopefully acceptable. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-20device_tree: s/qemu_devtree/qemu_fdt globallyPeter Crosthwaite3-74/+74
The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-17hw/arm: add cubieboard supportliguang2-1/+70
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-6-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm: add allwinner a10 SoC supportliguang2-0/+104
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add NOR ROM supportAntony Pavlov1-0/+78
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmail.com [PMM: don't try to load ROM blob if qtest_enabled()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add UART supportAntony Pavlov1-0/+16
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-5-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add timer supportAntony Pavlov1-0/+28
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-4-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: prepare DIGIC-based boards supportAntony Pavlov2-0/+85
Also this patch adds initial support for Canon PowerShot A1100 IS compact camera. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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