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2012-08-01target-i386: move cpu halted decision into x86_cpu_resetIgor Mammedov1-1/+4
MP initialization protocol differs between cpu families, and for P6 and onward models it is up to CPU to decide if it will be BSP using this protocol, so try to model this. However there is no point in implementing MP initialization protocol in qemu. Thus first CPU is always marked as BSP. This patch: - moves decision to designate BSP from board into cpu, making cpu self-sufficient in this regard. Later it will allow to cleanup hw/pc.c and remove cpu_reset and wrappers from there. - stores flag that CPU is BSP in IA32_APIC_BASE to model behavior described in Inted SDM vol 3a part 1 chapter 8.4.1 - uses MSR_IA32_APICBASE_BSP flag in apic_base for checking if cpu is BSP patch is based on Jan Kiszka's proposal: http://thread.gmane.org/gmane.comp.emulators.qemu/100806 Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-07-10apic: Defer interrupt updates to VCPU threadJan Kiszka1-0/+1
KVM performs TPR raising asynchronously to QEMU, specifically outside QEMU's global lock. When an interrupt is injected into the APIC and TPR is checked to decide if this can be delivered, a stale TPR value may be used, causing spurious interrupts in the end. Fix this by deferring apic_update_irq to the context of the target VCPU. We introduce a new interrupt flag for this, CPU_INTERRUPT_POLL. When it is set, the VCPU calls apic_poll_irq before checking for further pending interrupts. To avoid special-casing KVM, we also implement this logic for TCG mode. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2012-03-14i386 hw/: Don't use CPUStateAndreas Färber1-1/+1
Scripted conversion: for file in hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c hw/xen_machine_pv.c; do sed -i "s/CPUState/CPUX86State/g" $file done Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-18target-i386: Add infrastructure for reporting TPR MMIO accessesJan Kiszka1-0/+2
This will allow the APIC core to file a TPR access report. Depending on the accelerator and kernel irqchip mode, it will either be delivered right away or queued for later reporting. In TCG mode, we can restart the triggering instruction and can therefore forward the event directly. KVM does not allows us to restart, so we postpone the delivery of events recording in the user space APIC until the current instruction is completed. Note that KVM without in-kernel irqchip will report the address after the instruction that triggered the access. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2012-01-19apic: Factor out base class for KVM reuseJan Kiszka1-1/+0
The KVM in-kernel APIC model will reuse parts of the user space model while providing the same frontend view to guest and most management interfaces. Factor out an APIC base class to encapsulate those parts that will be shared by user space and KVM model. This class offers callback hooks for init, base/tpr setting, and the external NMI delivery that will be set via APICCommonInfo structure and implemented specifically in the subclasses. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Introduce apic_report_irq_deliveredJan Kiszka1-0/+1
The in-kernel i8259 and IOAPIC backends for KVM will need this, so encapsulate the shared bits. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-01-19apic: Inject external NMI events via LINT1Jan Kiszka1-0/+1
On real hardware, NMI button events are injected via the LINT1 line of the APICs. E.g. kdump expect this wiring and gets upset if the per-APIC LINT1 mask is not respected, i.e. if NMIs are injected to VCPUs that should not receive them. Change the APIC emulation code to reflect this. Based on qemu-kvm patch by Lai Jiangshan. CC: Lai Jiangshan <laijs@cn.fujitsu.com> Reported-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2011-08-22target-i386: Remove unused polarity arguments from APIC APIJan Kiszka1-4/+2
Polarity of external interrupts needs to be handled in the IOAPIC. Passing it to the APIC is pointless. So remove all these arguments. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-06-19apic: qdev conversion cleanupBlue Swirl1-12/+12
Make APICState completely private to apic.c by using DeviceState in external APIs. Move apic_init() to pc.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19apic: convert to qdevBlue Swirl1-1/+1
Convert to qdev. Use an opaque CPUState pointer because of missing VMState implementation for CPUState. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19apic: avoid using CPUState internalsBlue Swirl1-1/+9
Move the actual CPUState contents handling to cpu.h and cpuid.c. Handle CPU reset and set env->halted in pc.c. Add a function to get the local APIC state of the current CPU for the MMIO. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19apic: avoid passing CPUState from devicesBlue Swirl1-3/+5
Pass only APICState from pc.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-19ioapic: convert to qdevBlue Swirl1-2/+0
Convert to qdev. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-17ioapic: unexport ioapic_set_irqBlue Swirl1-1/+0
There's no need to use ioapic_set_irq() outside of ioapic.c, so make it static. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-21Move x86 specific PC declarations to a separate fileBlue Swirl1-0/+20
x86 definitions (especially CPUState uses) prevent many files from being compiled within libhw. Move x86 specific declarations (APIC stuff) to a separate file. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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