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2022-06-09hw/acpi/viot: sort VIOT ACPI table entries by PCI host bridge min_busMark Cave-Ayland1-0/+17
This ensures that the VIOT ACPI table output is always stable for a given PCI topology by ensuring that entries are ordered according to min_bus. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220525173232.31429-6-mark.cave-ayland@ilande.co.uk> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09hw/acpi/viot: build array of PCI host bridges before generating VIOT ACPI tableMark Cave-Ayland1-18/+24
Perform the generation of the VIOT ACPI table in 2 separate passes: the first pass enumerates all of the PCI host bridges and adds the min_bus and max_bus information to an array. Once this is done the VIOT table header is generated using the size of the array to calculate the node count, which means it is no longer necessary to use a sub-array to hold the PCI host bridge range information along with viommu_off. Finally the PCI host bridge array is iterated again to add the required entries to the final VIOT ACPI table. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220525173232.31429-4-mark.cave-ayland@ilande.co.uk> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09hw/acpi/viot: move the individual PCI host bridge entry generation to a new ↵Mark Cave-Ayland1-21/+27
function Instead of generating each table entry inline, move the individual PCI host bridge table entry generation to a separate build_pci_host_range() function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220525173232.31429-3-mark.cave-ayland@ilande.co.uk> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09hw/acpi/viot: rename build_pci_range_node() to enumerate_pci_host_bridges()Mark Cave-Ayland1-2/+2
This is in preparation for separating out the VIOT ACPI table build from the PCI host bridge numeration. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220525173232.31429-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-11-01hw/acpi: Add VIOT tableJean-Philippe Brucker1-0/+114
Add a function that generates a Virtual I/O Translation table (VIOT), describing the topology of paravirtual IOMMUs. The table is created if a virtio-iommu device is present. It contains a virtio-iommu node and PCI Range nodes for endpoints managed by the IOMMU. By default, a single node describes all PCI devices. When passing the "default_bus_bypass_iommu" machine option and "bypass_iommu" PXB option, only buses that do not bypass the IOMMU are described by PCI Range nodes. Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-Id: <20211026182024.2642038-2-jean-philippe@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>