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2024-07-03util/cpuinfo-riscv: Support host/cpuinfo.h for riscvRichard Henderson1-0/+23
Move detection code out of tcg, similar to other hosts. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-28Revert "host/i386: assume presence of SSE2"Paolo Bonzini2-2/+4
This reverts commit b18236897ca15c3db1506d8edb9a191dfe51429c. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-28Revert "host/i386: assume presence of POPCNT"Paolo Bonzini1-0/+1
This reverts commit 45ccdbcb24baf99667997fac5cf60318e5e7db51. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-19util/bufferiszero: Add loongarch64 vector accelerationRichard Henderson1-0/+143
Use inline assembly because no release compiler allows per-function selection of the ISA. Tested-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19util/bufferiszero: Split out host include filesRichard Henderson4-0/+211
Split out host/bufferiszero.h.inc for x86, aarch64 and generic in order to avoid an overlong ifdef ladder. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19util/loongarch64: Detect LASX vector supportRichard Henderson1-0/+1
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-05host/i386: assume presence of POPCNTPaolo Bonzini1-1/+0
QEMU now requires an x86-64-v2 host, which has the POPCNT instruction. Use it freely in TCG-generated code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-05host/i386: assume presence of SSE2Paolo Bonzini1-1/+0
QEMU now requires an x86-64-v2 host, which has SSE2. Use it freely in buffer_is_zero. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-05host/i386: assume presence of CMOVPaolo Bonzini1-1/+0
QEMU now requires an x86-64-v2 host, which always has CMOV. Use it freely in TCG generated code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-05host/i386: nothing looks at CPUINFO_SSE4Paolo Bonzini1-1/+0
The only user was the SSE4.1 variant of buffer_is_zero, which has been removed; code to compute CPUINFO_SSE4 is dead. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-04-26accel/tcg: Rename load-extract/store-insert headers using .h.inc suffixPhilippe Mathieu-Daudé7-0/+0
Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented in the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'store-insert-al16.h' as 'store-insert-al16.h.inc' and 'load-extract-al16-al8.h' as 'load-extract-al16-al8.h.inc'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424173333.96148-3-philmd@linaro.org>
2023-11-13host/include/generic/host/atomic128: Fix compilation problem with Clang 17Thomas Huth2-2/+2
When compiling QEMU with Clang 17 on a s390x, the compilation fails: In file included from ../accel/tcg/cputlb.c:32: In file included from /root/qemu/include/exec/helper-proto-common.h:10: In file included from /root/qemu/include/qemu/atomic128.h:62: /root/qemu/host/include/generic/host/atomic128-ldst.h:68:15: error: __sync builtin operation MUST have natural alignment (consider using __ atomic). [-Werror,-Wsync-alignment] 68 | } while (!__sync_bool_compare_and_swap_16(ptr_align, old, new.i)); | ^ In file included from ../accel/tcg/cputlb.c:32: In file included from /root/qemu/include/exec/helper-proto-common.h:10: In file included from /root/qemu/include/qemu/atomic128.h:61: /root/qemu/host/include/generic/host/atomic128-cas.h:36:11: error: __sync builtin operation MUST have natural alignment (consider using __a tomic). [-Werror,-Wsync-alignment] 36 | r.i = __sync_val_compare_and_swap_16(ptr_align, c.i, n.i); | ^ 2 errors generated. It's arguably a bug in Clang since we already use __builtin_assume_aligned() to tell the compiler that the pointer is properly aligned. But according to https://github.com/llvm/llvm-project/issues/69146 it seems like the Clang folks don't see an easy fix on their side and recommend to use a type declared with __attribute__((aligned(16))) to work around this problem. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1934 Message-ID: <20231108085954.313071-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-11-06host/include/loongarch64: Add atomic16 load and storeRichard Henderson3-0/+103
While loongarch64 does not have a 128-bit cmpxchg, it does have 128-bit atomic load and store via the vector unit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-6-richard.henderson@linaro.org>
2023-11-06util: Add cpuinfo for loongarch64Richard Henderson1-0/+21
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiajie Chen <c@jia.je> Message-Id: <20230916220151.526140-4-richard.henderson@linaro.org>
2023-09-20i386: spelling fixesMichael Tokarev1-1/+1
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-20ppc: spelling fixesMichael Tokarev1-1/+1
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2023-09-19Merge tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi1-0/+1
*: Delete checks for old host definitions tcg/loongarch64: Generate LSX instructions fpu: Add conversions between bfloat16 and [u]int8 fpu: Handle m68k extended precision denormals properly accel/tcg: Improve cputlb i/o organization accel/tcg: Simplify tlb_plugin_lookup accel/tcg: Remove false-negative halted assertion tcg: Add gvec compare with immediate and scalar operand tcg/aarch64: Emit BTI insns at jump landing pads [Resolved conflict between CPUINFO_PMULL and CPUINFO_BTI. --Stefan] * tag 'pull-tcg-20230915-2' of https://gitlab.com/rth7680/qemu: (39 commits) tcg: Map code_gen_buffer with PROT_BTI tcg/aarch64: Emit BTI insns at jump landing pads util/cpuinfo-aarch64: Add CPUINFO_BTI tcg: Add tcg_out_tb_start backend hook fpu: Handle m68k extended precision denormals properly fpu: Add conversions between bfloat16 and [u]int8 accel/tcg: Introduce do_st16_mmio_leN accel/tcg: Introduce do_ld16_mmio_beN accel/tcg: Merge io_writex into do_st_mmio_leN accel/tcg: Merge io_readx into do_ld_mmio_beN accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1 accel/tcg: Merge cpu_transaction_failed into io_failed plugin: Simplify struct qemu_plugin_hwaddr accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed accel/tcg: Split out io_prepare and io_failed accel/tcg: Simplify tlb_plugin_lookup target/arm: Use tcg_gen_gvec_cmpi for compare vs 0 tcg: Add gvec compare with immediate and scalar operand tcg/loongarch64: Implement 128-bit load & store tcg/loongarch64: Lower rotli_vec to vrotri ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-09-16util/cpuinfo-aarch64: Add CPUINFO_BTIRichard Henderson1-0/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15host/include/aarch64: Implement clmul.hRichard Henderson2-0/+42
Detect PMULL in cpuinfo; implement the accel hook. Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15host/include/i386: Implement clmul.hRichard Henderson3-0/+31
Detect PCLMUL in cpuinfo; implement the accel hook. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-15crypto: Add generic 64-bit carry-less multiply routineRichard Henderson1-0/+15
Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-25other architectures: spelling fixesMichael Tokarev1-1/+1
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-25arm: spelling fixesMichael Tokarev1-1/+1
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-08host/include/ppc: Implement aes-round.hRichard Henderson3-0/+184
Detect CRYPTO in cpuinfo; implement the accel hooks. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08host/include/aarch64: Implement aes-round.hRichard Henderson2-0/+206
Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08host/include/i386: Implement aes-round.hRichard Henderson3-0/+154
Detect AES in cpuinfo; implement the accel hooks. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesdec_ISB_ISR_AK_IMCRichard Henderson1-0/+3
Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey + InvMixColumns. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesdec_ISB_ISR_IMC_AKRichard Henderson1-0/+3
Add a primitive for InvSubBytes + InvShiftRows + InvMixColumns + AddRoundKey. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesenc_SB_SR_MC_AKRichard Henderson1-0/+3
Add a primitive for SubBytes + ShiftRows + MixColumns + AddRoundKey. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesdec_IMCRichard Henderson1-0/+2
Add a primitive for InvMixColumns. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesenc_MCRichard Henderson1-0/+2
Add a primitive for MixColumns. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesdec_ISB_ISR_AKRichard Henderson1-0/+4
Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08crypto: Add aesenc_SB_SR_AKRichard Henderson1-0/+16
Start adding infrastructure for accelerating guest AES. Begin with a SubBytes + ShiftRows + AddRoundKey primitive. Acked-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08util: Add cpuinfo-ppc.cRichard Henderson2-0/+30
Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10 is actually spelled PPC_FEATURE2_ARCH_3_1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20host/include/x86_64: Use __m128i for "x" constraintsRichard Henderson2-13/+20
The macOS catalina compiler produces an error for __int128_t as the type for allocation with SSE inline asm constraint. Create a new X86Int128Union type and use the vector type for all SSE register inputs and outputs. Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30accel/tcg: Add aarch64 store_atom_insert_al16Richard Henderson1-0/+47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8Richard Henderson1-0/+40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30accel/tcg: Add x86_64 load_atom_extract_al16_or_al8Richard Henderson1-0/+50
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30accel/tcg: Extract store_atom_insert_al16 to host headerRichard Henderson1-0/+50
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30accel/tcg: Extract load_atom_extract_al16_or_al8 to host headerRichard Henderson1-0/+45
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-30qemu/atomic128: Add x86_64 atomic128-ldst.hRichard Henderson1-0/+68
With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic load/store without cmpxchg16b. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23qemu/atomic128: Add runtime test for FEAT_LSE2Richard Henderson1-13/+40
With FEAT_LSE2, load and store of int128 is directly supported. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23qemu/atomic128: Improve cmpxchg fallback for atomic16_setRichard Henderson1-4/+7
Use __sync_bool_compare_and_swap_16 to control the loop, rather than a separate comparison. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23qemu/atomic128: Split atomic16_readRichard Henderson2-17/+35
Create both atomic16_read_ro and atomic16_read_rw. Previously we pretended that we had atomic16_read in system mode, because we "know" that all ram is always writable to the host. Now, expose read-only and read-write versions all of the time. For aarch64, do not fall back to __atomic_read_16 even if supported by the compiler, to work around a clang bug. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128Richard Henderson2-1/+3
These symbols will shortly become dynamic runtime tests and therefore not appropriate for the preprocessor. Use the matching CONFIG_* symbols for that purpose. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.hRichard Henderson2-10/+20
Not only the routines in ldst_atomicity.c.inc need markup, but also the ones in the headers. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23include/host: Split out atomic128-ldst.hRichard Henderson2-0/+106
Separates the aarch64-specific portion into its own file. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23include/host: Split out atomic128-cas.hRichard Henderson2-0/+86
Separates the aarch64-specific portion into its own file. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23util: Add cpuinfo-aarch64.cRichard Henderson1-0/+22
Move the code from tcg/. The only use of these bits so far is with respect to the atomicity of tcg operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-23util: Add i386 CPUINFO_ATOMIC_VMOVDQURichard Henderson1-0/+1
Add a bit to indicate when VMOVDQU is also atomic if aligned. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-11-16 23:08:35 +0000