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2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens2-0/+22
This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-19RISC-V: Add 64-bit gdb xml files.Jim Wilson4-3/+356
Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-19RISC-V: Add 32-bit gdb xml files.Jim Wilson3-0/+347
Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-05gdbstub: Fix i386/x86_64 machine description and add control registersDoug Gale6-257/+387
The machine description we send is being (silently) thrown on the floor by GDB and GDB silently uses the default machine description, because the xml parse fails on <feature> nested within <feature>. Changes to the xml in qemu source code have no effect. In addition, the default machine description has fs_base, which fails to be retrieved, which breaks the whole register window. Add it and the other control registers. Signed-off-by: Doug Gale <doug16k@gmail.com> Message-Id: <20190124040457.2546-1-doug16k@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-14s390x/gdb: add gs registersChristian Borntraeger1-0/+14
Let's provide the guarded storage registers via gdb server. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2017-06-21target-m68k: define 96bit FP registers for gdb on 680x0Laurent Vivier1-0/+21
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-5-laurent@vivier.eu>
2017-06-07target/i386: Add GDB XML description for SSE registersAbdallah Bouassida4-0/+140
Add an XML description for SSE registers (XMM+MXCSR) for both X86 and X86-64 architectures in the GDB stub: - configure: Define gdb_xml_files for the X86 targets (32 and 64bit). - gdb-xml/i386-32bit-sse.xml & gdb-xml/i386-64bit-sse.xml: The XML files that contain a description of the XMM + MXCSR registers. - gdb-xml/i386-32bit.xml & gdb-xml/i386-64bit.xml: wrappers that include the XML file of the core registers and the other XML file of the SSE registers. - target/i386/cpu.c: Modify the gdb_core_xml_file to the new XML wrapper, modify the gdb_num_core_regs to fit the registers number defined in each XML file. Signed-off-by: Abdallah Bouassida <abdallah.bouassida@lauterbach.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-05-05target/i386: Add GDB XML register description supportAbdallah Bouassida2-0/+138
This patch implements XML target description support for X86 and X86-64 architectures in the GDB stub, as the way with ARM and PowerPC: - gdb-xml/32bit-core.xml & gdb-xml/64bit-core.xml: Adding the XML target description files, these files are picked from GDB source code. - configure: Define gdb_xml_files for X86 targets. - target/i386/cpu.c: Define gdb_core_xml_file and gdb_arch_name to add XML awareness for this architecture, modify the gdb_num_core_regs to fit the registers number defined in each XML file. Signed-off-by: Abdallah Bouassida <abdallah.bouassida@lauterbach.com> Message-Id: <2b3c8119-1602-28c7-eab4-296593877103@lauterbach.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-01-30target-ppc: gdbstub: Add VSX supportAnton Blanchard1-0/+44
Add the XML and functions to get and set VSX registers. Signed-off-by: Anton Blanchard <anton@samba.org> (fixed little-endian guests) Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2015-10-02s390x/gdb: expose virtualization specific registersDavid Hildenbrand1-0/+18
Let's expose some virtual/fake registers as virtualization specific registers. Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Message-Id: <1443689387-34473-3-git-send-email-jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2015-09-07s390x/gdb: support reading/writing of control registersDavid Hildenbrand1-0/+26
Let's support reading and writing of control registers for kvm and tcg. We have to take care of flushing the tlb (tcg) and pushing the changed registers into kvm. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27gdb-xml: Include XML for s390 vector registersEric Farman1-0/+59
Include the vector registers XML file that is provided by gdb, and can be used by the qemu gdbserver interface. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-09-01s390x/gdb: add the feature xml files for s390xDavid Hildenbrand3-0/+81
This patch adds the relevant s390x feature xml files taken from gdb. Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
2013-12-17target-arm: Support fp registers in gdb stubPeter Maydell1-0/+86
Register the aarch64-fpu XML and implement the necessary read/write handlers so we can support reading and writing of FP registers in the gdb stub. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-09-10target-arm: Add AArch64 gdbstub supportAlexander Graf1-0/+46
We want to be able to debug AArch64 guests. So let's add the respective gdb stub functions and xml descriptions that allow us to do so. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-12-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org [PMM: dropped unused fp regs XML for now; moved 64 bit only functions to new gdbstub64.c; these are hooked up in AArch64CPU, not via ifdefs in ARMCPU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2009-07-12gdb-xml: fix hacks in powerpc register numberingNathan Froyd4-20/+2
The powerpc xml files contained a hack--an empty, non-existent register--for getting the register numbers to line up for newer (XML-aware) and older (non-XML-aware) GDB. While this hack worked in some cases, it didn't work in all cases, notably when the user used `finish' or `continue': GDB would attempt to read the non-existent register and QEMU would complain. This patch fixes things up properly. Instead of inserting a fake register, we explicitly declare the floating-point and SPE registers to start at 71. This action accomplishes the same thing as the nasty hack, except that now GDB never tries to fetch the non-existant register 70. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-03-07Work around QEMU GDB stub suboptimalityaurel322-0/+18
The current XML files claim, on floating point-supporting Power chips, that $f0 is register 70. This would be fine, except that register 70 for non-XML-aware GDB is FPSCR. More importantly, 70 is less than NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the "core" register reading routines, rather than the floating-point register read routine we registered with gdb_register_coprocessor. Therefore, when we are talking to an XML-aware GDB, we claim that register has zero width, which causes the rest of QEMU's GDB stub to send an error back to GDB, which causes GDB to be unable to read the floating-point registers. (The problem is also present for SPE registers and occurs in a slightly different way for Altivec registers.) The best way to fix this is to have the "core register" XML files for PPC32 and PPC64 claim that there is a 4-byte register 70, which causes $f0 to be register 71, and everything works just fine from that point forward. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6770 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-04The different VFP variants will never occur at the same time, and giving thempbrook2-2/+2
different names confuses GDB, so use org.gnu.gdb.arm.vfp for all of them. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6682 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-24target-ppc: Add XML files for PowerPC registersaurel325-0/+244
These files are nearly identical to the XML files provided with GDB. The only difference is that power-{fpu,spe}.xml do not assign register numbers; the internal QEMU machinery takes care of that. Define gdb_xml_files for ppc targets in configure as well. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6420 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-11Add GDB XML register description support.pbrook6-0/+244
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
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