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2022-10-17softfloat: logB(0) should raise divideByZero exceptionSong Gao1-0/+1
logB(0) should raise divideByZero exception from IEEE 754-2008 spec 7.3 Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220930024510.800005-4-gaosong@loongson.cn>
2022-08-31fpu: Add rebias bool, value and operationLucas Mateus Castro (alqotel)2-2/+21
Added the possibility of recalculating a result if it overflows or underflows, if the result overflow and the rebias bool is true then the intermediate result should have 3/4 of the total range subtracted from the exponent. The same for underflow but it should be added to the exponent of the intermediate number instead. Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220805141522.412864-2-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-20Merge tag 'pull-request-2022-07-20' of https://gitlab.com/thuth/qemu into ↵Peter Maydell1-2/+2
staging * Fixes for s390x floating point vector instructions # gpg: Signature made Wed 20 Jul 2022 08:14:50 BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-07-20' of https://gitlab.com/thuth/qemu: tests/tcg/s390x: test signed vfmin/vfmax target/s390x: fix NaN propagation rules target/s390x: fix handling of zeroes in vfmin/vfmax Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # fpu/softfloat-specialize.c.inc
2022-07-19fpu/softfloat: Add LoongArch specializations for pickNaN*Song Gao1-1/+25
The muladd (inf,zero,nan) case sets InvalidOp and returns the input value 'c', and prefer sNaN over qNaN, in c,a,b order. Binary operations prefer sNaN over qNaN and a,b order. Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220716085426.3098060-3-gaosong@loongson.cn> [rth: Add specialization for pickNaN] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-19target/s390x: fix NaN propagation rulesIlya Leoshkevich1-1/+2
s390x has the same NaN propagation rules as ARM, and not as x86. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20220713182612.3780050-3-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-26softfloat: Use FloatRelation for fracN_cmpRichard Henderson1-5/+7
Since the caller, partsN_compare, is now exclusively using FloatRelation, it's clearer to use it here too. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220401132240.79730-4-richard.henderson@linaro.org>
2022-04-26softfloat: Use FloatRelation within partsN_compareRichard Henderson1-4/+7
As the return type is FloatRelation, it's clearer to use the type for 'cmp' within the function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220401132240.79730-3-richard.henderson@linaro.org>
2022-04-26softfloat: Fix declaration of partsN_compareRichard Henderson1-4/+4
The declaration used 'int', while the definition used 'FloatRelation'. This should have resulted in a compiler error, but mysteriously didn't. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220401132240.79730-2-richard.henderson@linaro.org>
2022-04-20softfloat: add float128_to_int128Matheus Ferst1-0/+64
Implements float128_to_int128 based on parts_float_to_int logic. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-7-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20softfloat: add float128_to_uint128Matheus Ferst1-0/+65
Implements float128_to_uint128 based on parts_float_to_uint logic. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-6-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20softfloat: add int128_to_float128Matheus Ferst1-0/+29
Based on parts_sint_to_float, implements int128_to_float128 to convert a signed 128-bit value received through an Int128 argument. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220330175932.6995-5-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20softfloat: add uint128_to_float128Matheus Ferst1-0/+25
Based on parts_uint_to_float, implements uint128_to_float128 to convert an unsigned 128-bit value received through an Int128 argument. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-4-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2021-12-17softfloat: Add float64r32 arithmetic routinesRichard Henderson1-0/+110
These variants take a float64 as input, compute the result to infinite precision (as we do with FloatParts), round the result to the precision and dynamic range of float32, and then return the result in the format of float64. This is the operation PowerPC requires for its float32 operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17softfloat: Add flag specific to signaling nansRichard Henderson2-7/+15
PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17softfloat: Add flag specific to convert non-nan to intRichard Henderson1-7/+7
PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17softfloat: Add flag specific to sqrt(-x)Richard Henderson1-1/+1
PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17softfloat: Add flags specific to Inf / Inf and 0 / 0Richard Henderson1-5/+11
PowerPC has these flags, and it's easier to compute them here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17softfloat: Add flag specific to Inf * 0Richard Henderson2-8/+8
PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17softfloat: Add flag specific to Inf - InfRichard Henderson1-1/+2
PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-29softfloat: add APIs to handle alternative sNaN propagation for fmax/fminChih-Min Chao2-8/+36
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == NaN. The IEEE 754 spec allows both implementation and some architecture such as riscv choose different defintions in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01softfloat: Remove assertion preventing silencing of NaN in default-NaN modePeter Maydell1-1/+0
In commit a777d6033447a we added an assertion to parts_silence_nan() that prohibits calling float*_silence_nan() when in default-NaN mode. This ties together a property of the output ("do we generate a default NaN when the result is a NaN?") with an operation on an input ("silence this input NaN"). It's true that most of the time when in default-NaN mode you won't need to silence an input NaN, because you can just produce the default NaN as the result instead. But some functions like float*_maxnum() are defined to be able to work with quiet NaNs, so silencing an input SNaN is still reasonable. In particular, the upcoming implementation of MVE VMAXNMV would fall over this assertion if we didn't delete it. Delete the assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-15softfloat: Use _Generic instead of QEMU_GENERICRichard Henderson1-6/+10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210614233143.1221879-3-richard.henderson@linaro.org>
2021-06-13softfloat: Fix tp init in float32_exp2Richard Henderson1-1/+1
Typo in the conversion to FloatParts64. Fixes: 572c4d862ff2 Fixes: Coverity CID 1457457 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210607223812.110596-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11meson: Split out fpu/meson.buildRichard Henderson1-0/+1
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Use hard-float for {u}int64_to_float{32,64}Richard Henderson1-0/+28
For the normal case of no additional scaling, this reduces the profile contribution of int64_to_float64 to the testcase in the linked issue from 0.81% to 0.04%. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/134 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert modrem operations to FloatPartsRichard Henderson3-1243/+295
Rename to parts$N_modrem. This was the last use of a lot of the legacy infrastructure, so remove it as required. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move floatN_log2 to softfloat-parts.c.incRichard Henderson2-99/+152
Rename to parts$N_log2. Though this is partly a ruse, since I do not believe the code will succeed for float128 without work. Which is ok for now, because we do not need this for more than float32 and float64. Since berkeley-testfloat-3 doesn't support log2, compare float64_log2 vs the system log2. Fix the errors for inputs near 1.0: test: 3ff00000000000b0 +0x1.00000000000b0p+0 sf: 3d2fa00000000000 +0x1.fa00000000000p-45 libm: 3d2fbd422b1bd36f +0x1.fbd422b1bd36fp-45 Error in fraction: 32170028290927 ulp test: 3feec24f6770b100 +0x1.ec24f6770b100p-1 sf: bfad3740d13c9ec0 -0x1.d3740d13c9ec0p-5 libm: bfad3740d13c9e98 -0x1.d3740d13c9e98p-5 Error in fraction: 40 ulp Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert float32_exp2 to FloatPartsRichard Henderson1-30/+23
Keep the intermediate results in FloatParts instead of converting back and forth between float64. Use muladd instead of separate mul+add. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80 compare to FloatPartsRichard Henderson1-60/+22
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_scalbn to FloatPartsRichard Henderson1-39/+11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80 to integer to FloatPartsRichard Henderson1-294/+42
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80 float conversions to FloatPartsRichard Henderson2-384/+67
This is the last use of commonNaNT and all of the routines that use it, so remove all of them for Werror. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert integer to floatx80 to FloatPartsRichard Henderson1-45/+13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_round_to_int to FloatPartsRichard Henderson1-103/+13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_round to FloatPartsRichard Henderson1-4/+6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_sqrt to FloatPartsRichard Henderson1-71/+11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_div to FloatPartsRichard Henderson1-87/+13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_mul to FloatPartsRichard Henderson1-62/+14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Convert floatx80_add/sub to FloatPartsRichard Henderson1-203/+136
Since this is the first such, this includes all of the packing and unpacking routines as well. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Adjust parts_uncanon_normal for floatx80Richard Henderson1-6/+30
With floatx80_precision_x, the rounding happens across the break between words. Notice this case with frac_lsb = round_mask + 1 -> 0 and check the bits in frac_hi as needed. In addition, since frac_shift == 0, we won't implicitly clear round_mask via the right-shift, so explicitly clear those bits. This fixes rounding for floatx80_precision_[sd]. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Introduce Floatx80RoundPrecRichard Henderson1-15/+17
Use an enumeration instead of raw 32/64/80 values. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Reduce FloatFmtRichard Henderson2-20/+15
Remove frac_lsb, frac_lsbm1, roundeven_mask. Compute these from round_mask in parts$N_uncanon_normal. With floatx80, round_mask will not be tied to frac_shift. Everything else is easily computable. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Split out parts_uncanon_normalRichard Henderson2-27/+40
We will need to treat the non-normal cases of floatx80 specially, so split out the normal case that we can reuse. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move sqrt_float to softfloat-parts.c.incRichard Henderson2-152/+261
Rename to parts$N_sqrt. Reimplement float128_sqrt with FloatParts128. Reimplement with the inverse sqrt newton-raphson algorithm from musl. This is significantly faster than even the berkeley sqrt n-r algorithm, because it does not use division instructions, only multiplication. Ordinarily, changing algorithms at the same time as migrating code is a bad idea, but this is the only way I found that didn't break one of the routines at the same time. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move scalbn_decomposed to softfloat-parts.c.incRichard Henderson2-69/+55
Rename to parts$N_scalbn. Reimplement float128_scalbn with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move compare_floats to softfloat-parts.c.incRichard Henderson2-132/+133
Rename to parts$N_compare. Rename all of the intermediate functions to ftype_do_compare. Rename the hard-float functions to ftype_hs_compare. Convert float128 to FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Implement float128_(min|minnum|minnummag|max|maxnum|maxnummag)David Hildenbrand1-0/+13
The float128 implementation is straight-forward. Unfortuantely, we don't have any tests we can simply adjust/unlock. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20210517142739.38597-24-david@redhat.com> [rth: Update for changed parts_minmax return value] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move minmax_flags to softfloat-parts.c.incRichard Henderson2-130/+156
Rename to parts$N_minmax. Combine 3 bool arguments to a bitmask. Introduce ftype_minmax functions as a common optimization point. Fold bfloat16 expansions into the same macro as the other types. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move uint_to_float to softfloat-parts.c.incRichard Henderson2-50/+56
Rename to parts$N_uint_to_float. Reimplement uint64_to_float128 with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-03softfloat: Move int_to_float to softfloat-parts.c.incRichard Henderson2-98/+70
Rename to parts$N_sint_to_float. Reimplement int{32,64}_to_float128 with FloatParts128. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-11-17 01:03:44 +0000