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path: root/disas/riscv.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-07disas/riscv: Replace TABs with spaceMax Chou1-3/+3
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou1-0/+137
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou1-1/+13
2023-10-12disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14Alvin Chang1-2/+2
2023-07-19riscv/disas: Fix disas output of upper immediatesChristoph Müllner1-3/+16
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner1-0/+139
2023-07-10target/riscv: Add disas support for BF16 extensionsWeiwei Li1-0/+44
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner1-0/+69
2023-07-10disas/riscv: Add support for XVentanaCondOpsChristoph Müllner1-0/+4
2023-07-10disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner1-2/+26
2023-07-10disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner1-1/+8
2023-07-10disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner1-1/+1
2023-07-10disas/riscv: Move types/constants to new header fileChristoph Müllner1-269/+1
2023-06-13disas/riscv.c: Remove redundant parenthesesWeiwei Li1-109/+110
2023-06-13disas/riscv.c: Fix lines with over 80 charactersWeiwei Li1-61/+140
2023-06-13disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li1-370/+370
2023-06-13disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li1-4/+12
2023-06-13disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li1-1/+7
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li1-3/+7
2023-05-25disas/riscv: Decode czero.{eqz,nez}Richard Henderson1-0/+6
2023-05-05disas/riscv.c: add disasm support for Zc*Weiwei Li1-1/+227
2023-03-14Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin1-9/+10
2023-03-14disas/riscv: Fix slli_uw decodingIvan Klokov1-4/+4
2023-03-05disas/riscv Fix ctzw disassembleIvan Klokov1-1/+1
2023-02-07target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich1-4/+4
2022-10-14disas/riscv.c: rvv: Add disas support for vector instructionsYang Liu1-2/+1430
2022-09-27target/riscv: Remove sideleg and sedelegRahul Pathak1-2/+0
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot1-6/+21
2022-04-29disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructionsWeiwei Li1-1/+172
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot1-0/+5
2021-10-07disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich1-3/+154
2019-06-27disas/riscv: Fix `rdinstreth` constraintWladimir J. van der Laan1-2/+3
2019-06-27disas/riscv: Disassemble reserved compressed encodings as illegalMichael Clark1-17/+45
2019-04-18disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster1-1/+1
2019-03-19RISC-V: Remove unnecessary disassembler constraintsMichael Clark1-138/+0
2018-05-06RISC-V: Fix missing break statement in disassemblerMichael Clark1-1/+2
2018-05-06RISC-V: Include instruction hex in disassemblyMichael Clark1-19/+20
2018-03-28RISC-V: Fix incorrect disassembly for addiwMichael Clark1-1/+1
2018-03-07RISC-V DisassemblerMichael Clark1-0/+3048
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