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2019-01-17virtio: virtio 9p really requires CONFIG_VIRTFS to workJuan Quintela1-1/+1
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-01-17virtio: split virtio input host bits from virtio-pciJuan Quintela1-0/+1
For consistency with other devices, rename virtio_host_{initfn,pci_info} to virtio_input_host_{initfn,info}. Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-01-09default-configs: Enable USB support for RISC-V machinesAlistair Francis2-0/+2
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-03Merge remote-tracking branch ↵Peter Maydell2-2/+14
'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging RISC-V Changes for 3.2, Part 1 This pull request contains the first set of RISC-V patches I'd like to target for the 3.2 development cycle. It's really just a collection of bug fixes with one major new feature: PCIe can now be attached to RISC-V guests. This has passed my usual test of booting the latest Linux RC into a Fedora disk image on the virt machine. # gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-3.2-part1: MAINTAINERS: Mark RISC-V as Supported riscv/cpu: use device_class_set_parent_realize target/riscv/pmp.c: Fix pmp_decode_napot() sifive_uart: Implement interrupt pending register RISC-V: Enable second UART on sifive_e and sifive_u RISC-V: Fix PLIC pending bitfield reads RISC-V: Fix CLINT timecmp low 32-bit writes RISC-V: Add hartid and \n to interrupt logging sifive_u: Set 'clock-frequency' DT property for SiFive UART sifive_u: Add clock DT node for GEM ethernet riscv: Enable VGA and PCIE_VGA hw/riscv/virt: Connect the gpex PCIe hw/riscv/virt: Adjust memory layout spacing hw/riscv/virt: Increase the number of interrupts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-21spapr/xive: introduce a XIVE interrupt controllerCédric Le Goater1-0/+1
sPAPRXive models the XIVE interrupt controller of the sPAPR machine. It inherits from the XiveRouter and provisions storage for the routing tables : - Event Assignment Structure (EAS) - Event Notification Descriptor (END) The sPAPRXive model incorporates an internal XiveSource for the IPIs and for the interrupts of the virtual devices of the guest. This model is consistent with XIVE architecture which also incorporates an internal IVSE for IPIs and accelerator interrupts in the IVRE sub-engine. The sPAPRXive model exports two memory regions, one for the ESB trigger and management pages used to control the sources and one for the TIMA pages. They are mapped by default at the addresses found on chip 0 of a baremetal system. This is also consistent with the XIVE architecture which defines a Virtualization Controller BAR for the internal IVSE ESB pages and a Thread Managment BAR for the TIMA. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [dwg: Fold in field accessor fixes] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-12-21ppc/xive: introduce a XIVE interrupt source modelCédric Le Goater1-0/+1
The first sub-engine of the overall XIVE architecture is the Interrupt Virtualization Source Engine (IVSE). An IVSE can be integrated into another logic, like in a PCI PHB or in the main interrupt controller to manage IPIs. Each IVSE instance is associated with an Event State Buffer (ESB) that contains a two bit state entry for each possible event source. When an event is signaled to the IVSE, by MMIO or some other means, the associated interrupt state bits are fetched from the ESB and modified. Depending on the resulting ESB state, the event is forwarded to the IVRE sub-engine of the controller doing the routing. Each supported ESB entry is associated with either a single or a even/odd pair of pages which provides commands to manage the source: to EOI, to turn off the source for instance. On a sPAPR machine, the O/S will obtain the page address of the ESB entry associated with a source and its characteristic using the H_INT_GET_SOURCE_INFO hcall. On PowerNV, a similar OPAL call is used. The xive_source_notify() routine is in charge forwarding the source event notification to the routing engine. It will be filled later on. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-12-20riscv: Enable VGA and PCIE_VGAAlistair Francis2-0/+6
Enable compile support for VGA devices. This allows the user to conenct a display by adding '-device bochs-display -display sdl' to their command line argument. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20hw/riscv/virt: Connect the gpex PCIeAlistair Francis2-2/+8
Connect the gpex PCIe device based on the device tree included in the HiFive Unleashed ROM. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-11-08hw/ppc/spapr_rng: Introduce CONFIG_SPAPR_RNG switch for spapr_rng.cThomas Huth1-0/+1
The spapr-rng device is suboptimal when compared to virtio-rng, so users might want to disable it in their builds. Thus let's introduce a proper CONFIG switch to allow us to compile QEMU without this device. The function spapr_rng_populate_dt is required for linking, so move it to a different location. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-11-02hw/arm: versal: Add a model of Xilinx Versal SoCEdgar E. Iglesias1-0/+1
Add a model of Xilinx Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-30Merge remote-tracking branch ↵Peter Maydell2-1/+1
'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging QEMU trivial patches collected between June and October 2018 (Thank you to Thomas Huth) v2: fix 32bit build with updated patch (v3) from Philippe Mathieu-Daudé built in a 32bit debian sid chroot # gpg: Signature made Tue 30 Oct 2018 11:23:01 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request: milkymist-minimac2: Use qemu_log_mask(GUEST_ERROR) instead of error_report ppc: move at24c to its own CONFIG_ symbol hw/intc/gicv3: Remove useless parenthesis around DIV_ROUND_UP macro hw/pci-host: Remove useless parenthesis around DIV_ROUND_UP macro tests/bios-tables-test: Remove an useless cast xen: Use the PCI_DEVICE macro qobject: Catch another straggler for use of qdict_put_str() configure: Support pkg-config for zlib tests: Fix typos in comments and help message (found by codespell) cpu.h: fix a typo in comment linux-user: fix comment s/atomic_write/atomic_set/ qemu-iotests: make 218 executable scripts/qemu.py: remove trailing quotes on docstring scripts/decodetree.py: remove unused imports docs/devel/testing.rst: add missing newlines after code block qemu-iotests: fix filename containing checks tests/tcg/README: fix location for lm32 tests memory.h: fix typos in comments vga_int: remove unused function protype configs/alpha: Remove unused CONFIG_PARALLEL_ISA switch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-30ppc: move at24c to its own CONFIG_ symbolPaolo Bonzini1-0/+1
AT24c EEPROM is currently gated by CONFIG_I2C, and as such it is being included in all emulators that use I2C, even if they do not really need it. Separate it and, since it was added for the e500 machines, add it to qemu-system-ppc and qemu-system-ppc64. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20180522191743.12872-1-pbonzini@redhat.com> [lv: rebase] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-26configs/alpha: Remove unused CONFIG_PARALLEL_ISA switchThomas Huth1-1/+0
We don't use CONFIG_PARALLEL_ISA in any of our Makefiles, so this is just a dead config option which can be removed. Fixes: a4cb773928e047b137c6998209cf2eec857fac6b Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1540376314-5727-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-25Merge remote-tracking branch ↵Peter Maydell3-3/+4
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2018-10-25 * sysbus init/realize cleanups (Cédric Le Goater, Philippe Mathieu-Daudé) * memory-device refactoring (David Hildenbrand) * -smp: deprecate incorrect CPUs topology (Igor Mammedov) * -numa parsing cleanups (Markus Armbruster) * Fix hostmem-file memory leak (Zhang Yi) * Typo fix (Li Qiang) # gpg: Signature made Thu 25 Oct 2018 14:31:46 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: (43 commits) net: xgmac: convert SysBus init method to a realize method net: stellaris_enet: add a reset method net: stellaris_enet: convert SysBus init method to a realize method net: smc91c111: convert SysBus init method to a realize method net: opencores_eth: convert SysBus init method to a realize method net: mipsnet: convert SysBus init method to a realize method net: milkymist_minimac2: convert SysBus init method to a realize method net: lance: convert SysBus init method to a realize method net: lan9118: convert SysBus init method to a realize method net: etraxfs_eth: add a reset method net: etraxfs_eth: convert SysBus init method to a realize method memory-device: trace when pre_plugging/plugging/unplugging memory-device: complete factoring out unplug handling memory-device: complete factoring out plug handling memory-device: complete factoring out pre_plug handling memory-device: add device class function set_addr() memory-device: drop get_region_size() memory-device: factor out get_memory_region() from pc-dimm memory-device: add and use memory_device_get_region_size() memory-device: document MemoryDeviceClass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24memory-device: introduce separate config optionDavid Hildenbrand2-2/+4
Some architectures might support memory devices, while they don't support DIMM/NVDIMM. So let's - Rename CONFIG_MEM_HOTPLUG to CONFIG_MEM_DEVICE - Introduce CONFIG_DIMM and use it similarly to CONFIG NVDIMM CONFIG_DIMM and CONFIG_NVDIMM require CONFIG_MEM_DEVICE. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20181005092024.14344-7-david@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-10-24hw/sparc64/niagara: Model the I/O Bridge with the 'unimplemented_device'Philippe Mathieu-Daudé1-1/+0
Since the I/O Bridge device is not implemented, Use the TYPE_UNIMPLEMENTED_DEVICE which suits better: if the user asks for 'unimp' warnings via the -d option then all accesses will generate logging. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Message-Id: <20181002212522.23303-10-f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-10-24configs: Add a CONFIG_SMC37C669 switch for the "smc37c669-superio" deviceThomas Huth1-0/+1
This device is not user-creatable and currently only used for the "alpha" target. So if the user does not want to compile alpha-softmmu, we should also not compile this device. Add a proper config switch to be able to compile this more flexibly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-10-19default-configs: collect CONFIG_HYPERV* in hyperv.makRoman Kagan2-1/+3
Accumulate HYPERV config options in a dedicated file. There are only two so far; more will be added later. Signed-off-by: Roman Kagan <rkagan@virtuozzo.com> Message-Id: <20180921082041.29380-5-rkagan@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-15display: add separate config option for bochs-displayGerd Hoffmann1-0/+1
This allows modern architectures which don't care about vga compatibility (risc-v for example) build bochs-display without including all vga emulation too. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20181005160147.892-2-kraxel@redhat.com
2018-10-12s390x/vfio: ap: Introduce VFIO AP deviceTony Krowiak1-0/+1
Introduces a VFIO based AP device. The device is defined via the QEMU command line by specifying: -device vfio-ap,sysfsdev=<path-to-mediated-matrix-device> There may be only one vfio-ap device configured for a guest. The mediated matrix device is created by the VFIO AP device driver by writing a UUID to a sysfs attribute file (see docs/vfio-ap.txt). The mediated matrix device will be named after the UUID. Symbolic links to the $uuid are created in many places, so the path to the mediated matrix device $uuid can be specified in any of the following ways: /sys/devices/vfio_ap/matrix/$uuid /sys/devices/vfio_ap/matrix/mdev_supported_types/vfio_ap-passthrough/devices/$uuid /sys/bus/mdev/devices/$uuid /sys/bus/mdev/drivers/vfio_mdev/$uuid When the vfio-ap device is realized, it acquires and opens the VFIO iommu group to which the mediated matrix device is bound. This causes a VFIO group notification event to be signaled. The vfio_ap device driver's group notification handler will get called at which time the device driver will configure the the AP devices to which the guest will be granted access. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20181010170309.12045-6-akrowiak@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [CH: added missing g_free and device category] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-09-25arm: Add Nordic Semiconductor nRF51 SoCJoel Stanley1-0/+1
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-28ppc: Remove deprecated ppcemb targetThomas Huth1-23/+0
There is no known available OS for ppc around anymore that uses page sizes below 4k, so it does not make much sense that we keep wasting our time on building and testing the ppcemb-softmmu target. It has been deprecated since two releases, and nobody complained, so let's remove this now. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-08-27x86_64-softmmu: Configuration is identical to i386-softmmuJuan Quintela1-66/+1
If we ever changed that, just make the things that are different explicit. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2018-08-24hw/misc/tz-msc: Model TrustZone Master Security ControllerPeter Maydell1-0/+1
Implement a model of the TrustZone Master Securtiy Controller, as documented in the Arm CoreLink SIE-200 System IP for Embedded TRM (DDI0571G): https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g The MSC is intended to sit in front of a device which can be a bus master (eg a DMA controller) and programmably gate its transactions. This allows a bus-mastering device to be controlled by non-secure code but still restricted from making accesses to addresses which are secure-only. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/misc/iotkit-sysinfo: Implement IoTKit system information blockPeter Maydell1-0/+1
Implement the IoTKit system control element's system information block; this is just a pair of read-only version/config registers, plus the usual PID/CID ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-10-peter.maydell@linaro.org
2018-08-24hw/misc/iotkit-sysctl: Implement IoTKit system control elementPeter Maydell1-0/+1
The Arm IoTKit includes a system control element which provides a block of read-only ID registers and a block of read-write control registers. Implement a minimal version of this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-9-peter.maydell@linaro.org
2018-08-24hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer modulePeter Maydell1-0/+1
The Arm Cortex-M System Design Kit includes a "dual-input timer module" which combines two programmable down-counters. Implement a model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-4-peter.maydell@linaro.org
2018-08-20hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog modulePeter Maydell1-0/+1
The Arm Cortex-M System Design Kit includes a simple watchdog module based on a 32-bit down-counter. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16i.MX6UL: Add i.MX6UL SOCJean-Christophe Dubois1-0/+1
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-07sm501: Implement i2c part for reading monitor EDIDBALATON Zoltan4-0/+6
Emulate the i2c part of SM501 which is used to access the EDID info from a monitor. The vmstate structure is changed and its version is increased but SM501 is only used on SH and PPC sam460ex machines that don't support cross-version migration. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis2-0/+4
Connect the Cadence GEM ethernet device. This also requires us to expose the plic interrupt lines. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Clark <mjc@sifive.com>
2018-07-03ppc: Include vga cirrus card into the compiling processSebastian Bauer1-0/+1
Drivers for this card exists on PPC-based AmigaOS guests so it is useful to allow users to emulate the graphics card for PPC machines. As cirrus vga is currently preferred over std(vga) in absence of any user choice, this change also sets the default display of spapr machines to std as otherwise qemu refuses to start these machines. Not specifying an explicit graphics mode is for instance done by 'make check'. Signed-off-by: Sebastian Bauer <mail@sebastianbauer.info> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03hw/timer: Add basic M41T80 emulationBALATON Zoltan1-0/+1
Basic emulation of the M41T80 serial (I2C) RTC chip. Only getting time of day is implemented. Setting time and RTC alarm are not supported. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-03hw/ppc: Give sam46ex its own config optionDavid Gibson1-0/+1
At present the Sam460ex board is activated by the general CONFIG_PPC4XX option. However that includes the board for both ppc-softmmu and (deprecated) ppcemb-softmmu builds. As Sam460ex is developed, that would require adding more things into ppcemb-softmmu, which we don't want to do. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-06-22Merge remote-tracking branch ↵Peter Maydell1-0/+1
'remotes/pmaydell/tags/pull-target-arm-20180622' into staging target-arm queue: * hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR * target/arm: fix read of freed memory in kvm_arm_machine_init_done() * virt: support up to 512 CPUs * virt: support 256MB ECAM PCI region (for more PCI devices) * xlnx-zynqmp: Use Cortex-R5F, not Cortex-R5 * mps2-tz: Implement and use the TrustZone Memory Protection Controller * target/arm: enforce alignment checking for v6M cores * xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() * vl.c: Don't zero-initialize statics for serial_hds # gpg: Signature made Fri 22 Jun 2018 13:56:00 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180622: (28 commits) xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() vl.c: Don't zero-initialize statics for serial_hds target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline target/arm: Introduce ARM_FEATURE_M_MAIN hw/arm/mps2-tz.c: Instantiate MPCs hw/arm/iotkit: Wire up MPC interrupt lines hw/arm/iotkit: Instantiate MPC hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate hw/misc/tz-mpc.c: Implement correct blocked-access behaviour hw/misc/tz-mpc.c: Implement registers hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F target-arm: Add the Cortex-R5F hw/arm/virt: Increase max_cpus to 512 hw/arm/virt: Use 256MB ECAM region by default hw/arm/virt: Add virt-3.0 machine type hw/arm/virt: Add a new 256MB ECAM region hw/arm/virt: Register two redistributor regions when necessary hw/arm/virt-acpi-build: Advertise one or two GICR structures ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection ControllerPeter Maydell1-0/+1
Implement the Arm TrustZone Memory Protection Controller, which sits in front of RAM and allows secure software to configure it to either pass through or reject transactions. We implement the MPC as a QEMU IOMMU, which will direct transactions either through to the devices and memory behind it or to a special "never works" AddressSpace if they are blocked. This initial commit implements the skeleton of the device: * it always permits accesses * it doesn't implement most of the registers * it doesn't implement the interrupt or other behaviour for blocked transactions Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-2-peter.maydell@linaro.org
2018-06-21ppc4xx_i2c: Implement directcntl registerBALATON Zoltan2-0/+2
As well as being able to generate its own i2c transactions, the ppc4xx i2c controller has a DIRECTCNTL register which allows explicit control of the i2c lines. Using this register an OS can directly bitbang i2c operations. In order to let emulated i2c devices respond to this, we need to wire up the DIRECTCNTL register to qemu's bitbanged i2c handling code. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-06-16mac_newworld: add PMU deviceMark Cave-Ayland1-0/+1
The PMU device supercedes the CUDA device found on older New World Macs and is supported by a larger number of guest OSs from OS 9 to OS X 10.5. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-06-16mac_newworld: add gpios to macio devices with PMU enabledMark Cave-Ayland1-0/+1
PMU-enabled New World Macs expose their GPIOs via a separate memory region within the macio device. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-06-08misc: add pca9552 LED blinker modelCédric Le Goater1-0/+1
Specs are available here : https://www.nxp.com/docs/en/application-note/AN264.pdf This is a simple model supporting the basic registers for led and GPIO mode. The device also supports two blinking rates but not the model yet. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180530064049.27976-7-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01hw: make virtio devices configurable via default-configs/Paolo Bonzini7-13/+21
This is only half of the work, because the proxy devices (virtio-*-pci, virtio-*-ccw, etc.) are still included unconditionally. It is still a move in the right direction. Based-on: <20180522194943.24871-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-01hw: allow compiling out SCSIPaolo Bonzini7-0/+7
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-04hw/arm/smmu-common: smmu base device and datatypesEric Auger1-0/+1
The patch introduces the smmu base device and class for the ARM smmu. Devices for specific versions will be derived from this base device. We also introduce some important datatypes. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-17Merge remote-tracking branch 'remotes/xtensa/tags/20180316-xtensa' into stagingPeter Maydell2-0/+2
target/xtensa linux-user support. - small cleanup for xtensa registers dumping (-d cpu); - add support for debugging linux-user process with xtensa-linux-gdb (as opposed to xtensa-elf-gdb), which can only access unprivileged registers; - enable MTTCG for target/xtensa; - cleanup in linux-user/mmap area making sure that it works correctly with limited 30-bit-wide user address space; - import xtensa-specific definitions from the linux kernel, conditionalize user-only/softmmu-only code and add handlers for signals, exceptions, process/thread creation and core registers dumping. # gpg: Signature made Fri 16 Mar 2018 16:46:19 GMT # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180316-xtensa: MAINTAINERS: fix W: address for xtensa qemu-binfmt-conf.sh: add qemu-xtensa target/xtensa: add linux-user support linux-user: drop unused target_msync function linux-user: fix target_mprotect/target_munmap error return values linux-user: fix assertion in shmdt linux-user: fix mmap/munmap/mprotect/mremap/shmat target/xtensa: support MTTCG target/xtensa: use correct number of registers in gdbstub target/xtensa: mark register windows in the dump target/xtensa: dump correct physical registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # linux-user/syscall.c
2018-03-16target/xtensa: add linux-user supportMax Filippov2-0/+2
Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-16Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell3-0/+9
* Record-replay lockstep execution, log dumper and fixes (Alex, Pavel) * SCSI fix to pass maximum transfer size (Daniel Barboza) * chardev fixes and improved iothread support (Daniel Berrangé, Peter) * checkpatch tweak (Eric) * make help tweak (Marc-André) * make more PCI NICs available with -net or -nic (myself) * change default q35 NIC to e1000e (myself) * SCSI support for NDOB bit (myself) * membarrier system call support (myself) * SuperIO refactoring (Philippe) * miscellaneous cleanups and fixes (Thomas) # gpg: Signature made Mon 12 Mar 2018 16:10:52 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (69 commits) tcg: fix cpu_io_recompile replay: update documentation replay: save vmstate of the asynchronous events replay: don't process async events when warping the clock scripts/replay-dump.py: replay log dumper replay: avoid recursive call of checkpoints replay: check return values of fwrite replay: push replay_mutex_lock up the call tree replay: don't destroy mutex at exit replay: make locking visible outside replay code replay/replay-internal.c: track holding of replay_lock replay/replay.c: bump REPLAY_VERSION again replay: save prior value of the host clock replay: added replay log format description replay: fix save/load vm for non-empty queue replay: fixed replay_enable_events replay: fix processing async events cpu-exec: fix exception_index handling hw/i386/pc: Factor out the superio code hw/alpha/dp264: Use the TYPE_SMC37C669_SUPERIO ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # default-configs/i386-softmmu.mak # default-configs/x86_64-softmmu.mak
2018-03-13target/i386: add Secure Encrypted Virtualization (SEV) objectBrijesh Singh2-0/+2
Add a new memory encryption object 'sev-guest'. The object will be used to create encrypted VMs on AMD EPYC CPU. The object provides the properties to pass guest owner's public Diffie-hellman key, guest policy and session information required to create the memory encryption context within the SEV firmware. e.g to launch SEV guest # $QEMU \ -object sev-guest,id=sev0 \ -machine ....,memory-encryption=sev0 Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12hw/alpha/dp264: Use the TYPE_SMC37C669_SUPERIOPhilippe Mathieu-Daudé1-0/+3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180308223946.26784-25-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12hw/alpha/dp264: Add the ISA DMA controllerPhilippe Mathieu-Daudé1-0/+2
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180308223946.26784-24-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-12hw/i386: make IOMMUs configurable via default-configs/Paolo Bonzini2-0/+4
Allow distributions to disable the Intel and/or AMD IOMMU devices. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-01-01 18:21:46 +0000