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2021-11-04plugins/cache: make L2 emulation optional through argsMahmoud Mandour1-22/+54
By default L2 is not enabled and is enabled by either using the newly-introduced "l2" boolean argument, or by setting any of the L2 cache parameters using args. On specifying "l2=on", the default cache configuration is used. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-5-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-17-alex.bennee@linaro.org>
2021-11-04plugins/cache: split command line arguments into name and valueMahmoud Mandour1-27/+30
This way of handling args is more lenient and sets a better framework to parse boolean command line arguments. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-4-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-16-alex.bennee@linaro.org>
2021-11-04plugins/cache: implement unified L2 cache emulationMahmoud Mandour1-81/+175
This adds an implementation of a simple L2 configuration, in which a unified L2 cache (stores both blocks of instructions and data) is maintained for each core separately, with no inter-core interaction taken in account. The L2 cache is used as a backup for L1 and is only accessed if the wanted block does not exist in L1. In terms of multi-threaded user-space emulation, the same approximation of L1 is done, a static number of caches is maintained, and each and every memory access initiated by a thread will have to go through one of the available caches. An atomic increment is used to maintain the number of L2 misses per instruction. The default cache parameters of L2 caches is: 2MB cache size 16-way associativity 64-byte blocks Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-3-ma.mandourr@gmail.com> Message-Id: <20211026102234.3961636-15-alex.bennee@linaro.org>
2021-11-04plugins/cache: freed heap-allocated mutexesMahmoud Mandour1-0/+3
Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210810134844.166490-2-ma.mandourr@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211026102234.3961636-14-alex.bennee@linaro.org>
2021-09-02plugins/cache: supported multicore cache modellingMahmoud Mandour1-44/+132
Multicore L1 cache modelling is introduced and is supported for both full system emulation and linux-user. For full-system emulation, L1 icache and dcache are maintained for each available core, since this information is exposed to the plugin through `qemu_plugin_n_vcpus()`. For linux-user, a static number of cores is assumed (default 1 core, and can be provided as a plugin argument `cores=N`). Every memory access goes through one of these caches, this approach is taken as it's somewhat akin to what happens on real setup, where a program that dispatches more threads than the available cores, they'll thrash each other Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Message-Id: <20210803151301.123581-2-ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2021-07-23plugins/cache: Fixed "function decl. is not a prototype" warningsMahmoud Mandour1-3/+3
Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210714172151.8494-7-ma.mandourr@gmail.com> Message-Id: <20210720232703.10650-24-alex.bennee@linaro.org>
2021-07-23plugins/cache: limited the scope of a mutex lockMahmoud Mandour1-2/+1
It's not necessary to lock the address translation portion of the vcpu_mem_access callback. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210714172151.8494-3-ma.mandourr@gmail.com> Message-Id: <20210720232703.10650-23-alex.bennee@linaro.org>
2021-07-23plugins/cache: Fixed a bug with destroying FIFO metadataMahmoud Mandour1-1/+1
This manifests itself when associativity degree is greater than the number of sets and FIFO is used, otherwise it's also a memory leak whenever FIFO was used. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210714172151.8494-2-ma.mandourr@gmail.com> Message-Id: <20210720232703.10650-22-alex.bennee@linaro.org>
2021-07-14plugins/cache: Added FIFO and LRU eviction policiesMahmoud Mandour1-13/+190
Implemented FIFO and LRU eviction policies. Now one of the three eviction policies can be chosen as an argument. On not specifying an argument, LRU is used by default. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210623125458.450462-4-ma.mandourr@gmail.com> Message-Id: <20210709143005.1554-39-alex.bennee@linaro.org>
2021-07-14plugins/cache: Enable cache parameterizationMahmoud Mandour1-1/+46
Enabled configuring both icache and dcache parameters using plugin parameters. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210623125458.450462-3-ma.mandourr@gmail.com> Message-Id: <20210709143005.1554-38-alex.bennee@linaro.org>
2021-07-14plugins: Added a new cache modelling pluginMahmoud Mandour1-0/+419
Added a cache modelling plugin that uses a static configuration used in many of the commercial microprocessors and uses random eviction policy. The purpose of the plugin is to identify the most cache-thrashing instructions for both instruction cache and data cache. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210623125458.450462-2-ma.mandourr@gmail.com> Message-Id: <20210709143005.1554-37-alex.bennee@linaro.org>
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