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2025-03-06accel/tcg: Build tcg_flags helpers as common codePhilippe Mathieu-Daudé2-32/+33
While cpu-exec.c is build for each target,tcg_flags helpers aren't target specific. Move them to cpu-exec-common.c to build them once. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-8-philmd@linaro.org>
2025-03-06accel/accel: Make TYPE_ACCEL abstractPhilippe Mathieu-Daudé1-0/+1
There is no generic acceleration, we have to use specific implementations. Make the base class abstract. Fixes: b14a0b7469fa ("accel: Use QOM classes for accel types") Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200129212345.20547-3-philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-06gdbstub: Check for TCG before calling tb_flush()Philippe Mathieu-Daudé1-4/+0
Use the tcg_enabled() check so the compiler can elide the call when TCG isn't available, allowing to remove the tb_flush() stub. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-4-philmd@linaro.org>
2025-03-04hw/xen: Link XenPVH with GPEX PCIe bridgePhilippe Mathieu-Daudé1-0/+1
XenPVH requires the PCIe/GPEX device. Add it to Kconfig to avoid when configuring using --without-default-devices: /usr/bin/ld: libqemu-aarch64-softmmu.a.p/hw_xen_xen-pvh-common.c.o: in function `xenpvh_gpex_init': hw/xen/xen-pvh-common.c:174: undefined reference to `gpex_set_irq_num' /usr/bin/ld: libqemu-aarch64-softmmu.a.p/hw_xen_xen-hvm-common.c.o: in function `pci_dev_bus_num': include/hw/pci/pci.h:337: undefined reference to `pci_bus_num' /usr/bin/ld: include/hw/pci/pci.h:337: undefined reference to `pci_bus_num' /usr/bin/ld: include/hw/pci/pci.h:337: undefined reference to `pci_bus_num' /usr/bin/ld: include/hw/pci/pci.h:337: undefined reference to `pci_bus_num' /usr/bin/ld: include/hw/pci/pci.h:337: undefined reference to `pci_bus_num' /usr/bin/ld: libqemu-aarch64-softmmu.a.p/hw_xen_xen-hvm-common.c.o: in function `cpu_ioreq_config': hw/xen/xen-hvm-common.c:412: undefined reference to `pci_host_config_read_common' /usr/bin/ld: hw/xen/xen-hvm-common.c:428: undefined reference to `pci_host_config_read_common' /usr/bin/ld: hw/xen/xen-hvm-common.c:438: undefined reference to `pci_host_config_write_common' Fixes: f22e598a72c ("hw/xen: pvh-common: Add support for creating PCIe/GPEX") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20250218162618.46167-2-philmd@linaro.org>
2025-02-19Merge tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2-31/+10
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS tcg: Cleanups after disallowing 64-on-32 tcg: Introduce constraint for zero register tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 linux-user: Move TARGET_SA_RESTORER out of generic/signal.h linux-user: Fix alignment when unmapping excess reservation target/sparc: Fix register selection for all F*TOx and FxTO* instructions target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: fake UltraSPARC T1 PCR and PIC registers # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAme0tZ8dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+u+AgAi47VyMpkM8HvlvrV # 6NGYD5FANLAF+Axl42GCTZEsisLN8b+KNWnM3QIxtE/ryxVY+OBpn/JpMRN96MJH # jcbsbnadJxJEUktCi1Ny/9vZGKh/wfT45OdJ7Ej+J5J/5EIuDsJQEPlR5U4QVv7H # I574hNttTibj12lYs0lbo0hESIISL+ALNw+smBNYEQ5zZTAPl3utP96NiQ/w3lyK # qtybkljYXQRjOtUM7iNH2x6mwrBrPfbTDFubD0lLJGBTRQg2Q2Z5QVSsP4OY5gMp # L9NPEQPs35GXA8c0GcAWwhO6kAcEbvkcUEL+jhfalb5BWhVWBgmTqCqYXr5RvuG2 # flSRwg== # =BWCN # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Feb 2025 00:30:23 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu: (28 commits) tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 target/sparc: fake UltraSPARC T1 PCR and PIC registers target/sparc: Fix gdbstub incorrectly handling registers f32-f62 target/sparc: Fix register selection for all F*TOx and FxTO* instructions linux-user: Move TARGET_SA_RESTORER out of generic/signal.h elfload: Fix alignment when unmapping excess reservation tcg/sparc64: Use 'z' constraint tcg/riscv: Use 'z' constraint tcg/mips: Use 'z' constraint tcg/loongarch64: Use 'z' constraint tcg/aarch64: Use 'z' constraint tcg: Introduce the 'z' constraint for a hardware zero register include/exec: Use uintptr_t in CPUTLBEntry include/exec: Change vaddr to uintptr_t target/mips: Use VADDR_PRIx for logging pc_next target/loongarch: Use VADDR_PRIx for logging pc_next accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page plugins: Fix qemu_plugin_read_memory_vaddr parameters tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-18include/exec: Use uintptr_t in CPUTLBEntryRichard Henderson1-17/+4
Since we no longer support 64-bit guests on 32-bit hosts, we can use a 32-bit type on a 32-bit host. This shrinks the size of the structure to 16 bytes on a 32-bit host. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-18accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_pageRichard Henderson1-2/+2
The declarations use vaddr for size. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-18tcg: Remove TCG_OVERSIZED_GUESTRichard Henderson2-12/+4
This is now prohibited in configuration. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-12system/physmem: handle hugetlb correctly in qemu_ram_remap()William Roche1-1/+1
The list of hwpoison pages used to remap the memory on reset is based on the backend real page size. To correctly handle hugetlb, we must mmap(MAP_FIXED) a complete hugetlb page; hugetlb pages cannot be partially mapped. Signed-off-by: William Roche <william.roche@oracle.com> Co-developed-by: David Hildenbrand <david@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20250211212707.302391-2-william.roche@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com>
2025-02-08meson: Drop tcg as a moduleRichard Henderson1-7/+4
This reverts commit dae0ec159f9 ("accel: build tcg modular"). The attempt was only enabled for x86, only modularized a small portion of tcg, and in more than 3 years there have been no follow-ups to improve the situation. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-30licenses: Remove SPDX tags not being license identifier for LinaroPhilippe Mathieu-Daudé1-2/+7
Per [*]: "we're only interested in adopting SPDX for recording the licensing info, [not] any other SPDX metadata." Replace the 'SPDX-FileCopyrightText' and 'SPDX-FileContributor' tags added by Linaro by 'Copyright (c)' and 'Authors' words respectively. [*] https://lore.kernel.org/qemu-devel/20241007154548.1144961-4-berrange@redhat.com/ Inspired-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-01-21Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi3-10/+33
tcg: - Add TCGOP_TYPE, TCGOP_FLAGS. - Pass type and flags to tcg_op_supported, tcg_target_op_def. - Split out tcg-target-has.h and unexport from tcg.h. - Reorg constraint processing; constify TCGOpDef. - Make extract, sextract, deposit opcodes mandatory. - Merge ext{8,16,32}{s,u} opcodes into {s}extract. tcg/mips: Expand bswap unconditionally tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv: Use BEXTI for single-bit extractions tcg/sparc64: Use SRA, SRL for {s}extract_i64 disas/riscv: Guard dec->cfg dereference for host disassemble util/cpuinfo-riscv: Detect Zbs accel/tcg: Call tcg_tb_insert() for one-insn TBs linux-user: Add missing /proc/cpuinfo fields for sparc # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmeKnzUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+Kvgf+LG9UjXlWF9GK923E # TllBL2rLf1OOdtTXWO15VcvGMoWDwB3tVBdhihdvXmnWju+WbfMk6mct5NhzsKn9 # LmuugMIZs+hMROj+bgMK8x47jRIh5N2rDYxcEgmyfIpYb2o9qvyqKecGVRlSJTCE # bmt5UFbvPThBb8upoMfq3F6evuMx0szBP7wrOwSR/VGpmzIr20UTEWo6I1ALp4uj # paFaysYol4em3dIhkiuV9cL7E0EIObaNa7l9RUci/BmTq+JaVxUnW1Y2i0PEwKwG # FJSfYTJk3wBgAVxC2zC2g3ZM7uKuecSXMpiFopTiuyQLp7Q61i9kCNvEq0qY5tdb # DaqR/g== # =cv4O # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Jan 2025 13:19:33 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu: (68 commits) softfloat: Constify helpers returning float_status field accel/tcg: Call tcg_tb_insert() for one-insn TBs tcg: Document tb_lookup() and tcg_tb_lookup() linux-user: Add missing /proc/cpuinfo fields for sparc tcg/riscv: Use BEXTI for single-bit extractions util/cpuinfo-riscv: Detect Zbs tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} tcg/tci: Remove assertions for deposit and extract tcg/tci: Provide TCG_TARGET_{s}extract_valid tcg/sparc64: Use SRA, SRL for {s}extract_i64 tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/arm: Add full [US]XT[BH] into {s}extract tcg/aarch64: Expand extract with offset 0 with andi tcg/aarch64: Provide TCG_TARGET_{s}extract_valid ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-17accel/tcg: Call tcg_tb_insert() for one-insn TBsIlya Leoshkevich1-9/+18
Currently one-insn TBs created from I/O memory are not added to region_trees. Therefore, when they generate exceptions, they are not handled by cpu_restore_state_from_tb(). For x86 this is not a problem, because x86_restore_state_to_opc() only restores pc and cc, which already have the correct values if the first TB instruction causes an exception. However, on several other architectures, restore_state_to_opc() is not stricly limited to state restoration and affects some exception-related registers, where guests can notice incorrect values, for example: - arm's exception.syndrome; - hppa's unwind_breg; - riscv's excp_uw2; - s390x's int_pgm_ilen. Fix by always calling tcg_tb_insert(). This may increase the size of region_trees, but tcg_region_reset_all() clears it once code_gen_buffer fills up, so it will not grow uncontrollably. Do not call tb_link_page(), which would add such TBs to the QHT, to prevent tb_lookup() from finding them. These TBs are single-use, since subsequent reads from I/O memory may return different values; they are not removed from code_gen_buffer only in order to keep things simple. Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250116213214.5695-2-iii@linux.ibm.com>
2025-01-17tcg: Document tb_lookup() and tcg_tb_lookup()Ilya Leoshkevich1-1/+14
These similarly named functions serve different purposes; add docstrings to highlight them. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250116213214.5695-1-iii@linux.ibm.com>
2025-01-17accel/tcg: also suppress asynchronous IRQs for cpu_io_recompileAlex Bennée1-2/+3
While it would be technically correct to allow an IRQ to happen (as the offending instruction never really completed) it messes up instrumentation. We already take care to only use memory instrumentation on the block, we should also suppress IRQs. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Julian Ganz <neither@nut.email> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-23-alex.bennee@linaro.org>
2025-01-16tcg: Split out tcg-target-mo.hRichard Henderson1-0/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-09qdev: Implement qdev_create_fake_machine() for user emulationPhilippe Mathieu-Daudé1-1/+7
When a QDev instance is realized, qdev_get_machine() ends up called. In the next commit, qdev_get_machine() will require a "machine" container to be always present. To satisfy this QOM containers design, Implement qdev_create_fake_machine() which creates a fake "machine" container for user emulation. On system emulation, qemu_create_machine() is called from qemu_init(). For user emulation, since the TCG accelerator always calls tcg_init_machine(), we use it to hook our fake machine creation. Suggested-by: Peter Xu <peterx@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Peter Xu <peterx@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250102211800.79235-2-philmd@linaro.org>
2024-12-24accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_coreRichard Henderson2-6/+10
Convert all targets simultaneously, as the gen_intermediate_code function disappears from the target. While there are possible workarounds, they're larger than simply performing the conversion. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-24plugins: optimize cpu_index code generationPierrick Bouvier1-0/+9
When running with a single vcpu, we can return a constant instead of a load when accessing cpu_index. A side effect is that all tcg operations using it are optimized, most notably scoreboard access. When running a simple loop in user-mode, the speedup is around 20%. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241128213843.1023080-1-pierrick.bouvier@linaro.org>
2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi32-116/+167
Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-20accel/tcg: Un-inline translator_is_same_page()Philippe Mathieu-Daudé1-1/+6
Remove the single target-specific definition used in "exec/translator.h" (TARGET_PAGE_MASK) by un-inlining is_same_page(). Rename the method as translator_is_same_page() and improve its documentation. Use it in translator_use_goto_tb(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241218154145.71353-1-philmd@linaro.org>
2024-12-20accel/tcg: Include missing 'exec/translation-block.h' headerPhilippe Mathieu-Daudé2-0/+2
TB compile flags, tb_page_addr_t type, tb_cflags() and few other methods are defined in "exec/translation-block.h". All these files don't include "exec/translation-block.h" but include "exec/exec-all.h" which include it. Explicitly include "exec/translation-block.h" to be able to remove it from "exec/exec-all.h" later when it won't be necessary. Otherwise we'd get errors such: accel/tcg/internal-target.h:59:20: error: a parameter list without types is only allowed in a function definition 59 | void tb_lock_page0(tb_page_addr_t); | ^ accel/tcg/tb-hash.h:64:23: error: unknown type name 'tb_page_addr_t' 64 | uint32_t tb_hash_func(tb_page_addr_t phys_pc, vaddr pc, | ^ accel/tcg/tcg-accel-ops.c:62:36: error: use of undeclared identifier 'CF_CLUSTER_SHIFT' 62 | cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; | ^ accel/tcg/watchpoint.c:102:47: error: use of undeclared identifier 'CF_NOIRQ' 102 | cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); | ^ target/i386/helper.c:536:28: error: use of undeclared identifier 'CF_PCREL' 536 | if (tcg_cflags_has(cs, CF_PCREL)) { | ^ target/rx/cpu.c:51:21: error: incomplete definition of type 'struct TranslationBlock' 51 | cpu->env.pc = tb->pc; | ~~^ system/physmem.c:2977:9: error: call to undeclared function 'tb_invalidate_phys_range'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 2977 | tb_invalidate_phys_range(addr, addr + length - 1); | ^ plugins/api.c:96:12: error: call to undeclared function 'tb_cflags'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 96 | return tb_cflags(tcg_ctx->gen_tb) & CF_MEMI_ONLY; | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241114011310.3615-5-philmd@linaro.org>
2024-12-20accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'Philippe Mathieu-Daudé3-0/+3
The TranslationBlock flags are defined in 'exec/translation-block.h'. tcg_cflags_has/set() use them, it is more logical to declare them in the same place. Move them there too. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212144430.66224-2-philmd@linaro.org>
2024-12-20accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h'Philippe Mathieu-Daudé2-0/+4
curr_cflags() is only used within accel/tcg/, move its declaration to accel/tcg/internal-common.h. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241216214030.59393-1-philmd@linaro.org>
2024-12-20accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h'Philippe Mathieu-Daudé1-1/+1
Move cpu_loop_exit_requested() declaration to "exec/cpu-common.h", along with the related cpu_loop_exit_noexc(), cpu_loop_exit(), cpu_loop_exit_atomic() and cpu_loop_exit_restore() methods. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241217140648.98538-1-philmd@linaro.org>
2024-12-20user: Move various declarations out of 'exec/exec-all.h'Philippe Mathieu-Daudé1-0/+1
Move various declarations related to user emulation from "exec/exec-all.h" to "user/cpu_loop.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-19-philmd@linaro.org>
2024-12-20accel/tcg: Move user-related declarations out of 'exec/cpu-all.h' (4/4)Philippe Mathieu-Daudé1-0/+3
Move declarations related to page protection under user emulation from "exec/cpu-all.h" to "user/page-protection.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-15-philmd@linaro.org>
2024-12-20accel/tcg: Really restrict cpu_io_recompile() to system emulationPhilippe Mathieu-Daudé1-2/+2
Commit 38fc4b11e03 ("accel/tcg: Restrict cpu_io_recompile() to system emulation") inadvertently restricted cpu_io_recompile() to SoftMMU. Correct to restrict to system emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241216160514.56630-1-philmd@linaro.org>
2024-12-20accel/tcg: Move TranslationBlock declarations to 'tb-internal.h'Philippe Mathieu-Daudé7-32/+44
Move declarations related to TranslationBlock out of the generic "internal-target.h" to "tb-internal.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-11-philmd@linaro.org>
2024-12-20accel/tcg: Un-inline log_pc()Philippe Mathieu-Daudé2-10/+11
log_pc() is only used within cpu-exec.c, no need to expose it via "internal-target.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-10-philmd@linaro.org>
2024-12-20accel/tcg: Move 'exec/translate-all.h' -> 'tb-internal.h'Philippe Mathieu-Daudé7-5/+20
"exec/translate-all.h" is only useful to TCG accelerator, so move it to accel/tcg/, after renaming it 'tb-internal.h'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-9-philmd@linaro.org>
2024-12-20accel/tcg: Move page_[un]protect() to 'user/page-protection.h'Philippe Mathieu-Daudé2-1/+2
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-7-philmd@linaro.org>
2024-12-20accel/tcg: Use tb_page_addr_t type in page_unprotect()Philippe Mathieu-Daudé1-1/+1
Match with the page_protect() prototype, use a tb_page_addr_t argument instead of target_ulong. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-6-philmd@linaro.org>
2024-12-20accel/tcg: Declare mmap_[un]lock() in 'exec/page-protection.h'Philippe Mathieu-Daudé3-0/+3
Move mmap_lock(), mmap_unlock() declarations and the WITH_MMAP_LOCK_GUARD() definition to 'exec/page-protection.h'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-5-philmd@linaro.org>
2024-12-20accel/tcg: Have tlb_vaddr_to_host() use vaddr typePhilippe Mathieu-Daudé1-1/+1
abi_ptr is expected to be used in user emulation. tlb_vaddr_to_host() uses it, but can be used in system emulation. Replace the type by 'vaddr' which is equivalent on user emulation but also works on system. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241114011310.3615-13-philmd@linaro.org>
2024-12-20accel/tcg: Include missing 'exec/tswap.h' header in translator.cPhilippe Mathieu-Daudé1-0/+1
translator.c indirectly gets "exec/tswap.h" declarations via "exec/cpu-all.h". Include it directly to be able to remove the former from the latter, otherwise we get: accel/tcg/translator.c:433:15: error: call to undeclared function 'tswap16'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 433 | tgt = tswap16(raw); | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241211230357.97036-4-philmd@linaro.org>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé25-63/+63
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-12-19target/i386: Reset TSCs of parked vCPUs too on VM resetMaciej S. Szmigiero1-0/+11
Since commit 5286c3662294 ("target/i386: properly reset TSC on reset") QEMU writes the special value of "1" to each online vCPU TSC on VM reset to reset it. However parked vCPUs don't get that handling and due to that their TSCs get desynchronized when the VM gets reset. This in turn causes KVM to turn off PVCLOCK_TSC_STABLE_BIT in its exported PV clock. Note that KVM has no understanding of vCPU being currently parked. Without PVCLOCK_TSC_STABLE_BIT the sched clock is marked unstable in the guest's kvm_sched_clock_init(). This causes a performance regressions to show in some tests. Fix this issue by writing the special value of "1" also to TSCs of parked vCPUs on VM reset. Reproducing the issue: 1) Boot a VM with "-smp 2,maxcpus=3" or similar 2) device_add host-x86_64-cpu,id=vcpu,node-id=0,socket-id=0,core-id=2,thread-id=0 3) Wait a few seconds 4) device_del vcpu 5) Inside the VM run: # echo "t" >/proc/sysrq-trigger; dmesg | grep sched_clock_stable Observe the sched_clock_stable() value is 1. 6) Reboot the VM 7) Once the VM boots once again run inside it: # echo "t" >/proc/sysrq-trigger; dmesg | grep sched_clock_stable Observe the sched_clock_stable() value is now 0. Fixes: 5286c3662294 ("target/i386: properly reset TSC on reset") Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Link: https://lore.kernel.org/r/5a605a88e9a231386dc803c60f5fed9b48108139.1734014926.git.maciej.szmigiero@oracle.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19kvm: consistently return 0/-errno from kvm_convert_memoryPaolo Bonzini1-4/+4
In case of incorrect parameters, kvm_convert_memory() was returning -1 instead of -EINVAL. The guest won't notice because it will move anyway to RUN_STATE_INTERNAL_ERROR, but fix this for consistency and clarity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-12tcg: Reset free_temps before tcg_optimizeRichard Henderson1-1/+1
When allocating new temps during tcg_optmize, do not re-use any EBB temps that were used within the TB. We do not have any idea what span of the TB in which the temp was live. Introduce tcg_temp_ebb_reset_freed and use before tcg_optimize, as well as replacing the equivalent in plugin_gen_inject and tcg_func_start. Cc: qemu-stable@nongnu.org Fixes: fb04ab7ddd8 ("tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2711 Reported-by: wannacu <wannacu2049@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-16accel/tcg: Fix user-only probe_access_internal plugin checkRichard Henderson1-1/+1
The acc_flag check for write should have been against PAGE_WRITE_ORG, not PAGE_WRITE. But it is better to combine two acc_flag checks to a single check against access_type. This matches the system code in cputlb.c. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2647 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: 20241111145002.144995-1-richard.henderson@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2024-11-04Merge tag 'migration-20241030-pull-request' of ↵Peter Maydell1-1/+0
https://gitlab.com/peterx/qemu into staging Migration pull request for softfreeze v2: - Patch "migration: Move cpu-throttle.c from system to migration", fix build on MacOS, and subject spelling NOTE: checkpatch.pl could report a false positive on this branch: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #21: {include/sysemu => migration}/cpu-throttle.h | 0 That's covered by "F: migration/" entry. Changelog: - Peter's cleanup patch on migrate_fd_cleanup() - Peter's cleanup patch to introduce thread name macros - Hanna's error path fix for vmstate subsection save()s - Hyman's auto converge enhancement on background dirty sync - Peter's additional tracepoints for save state entries - Thomas's build fix for OpenBSD in dirtyrate.c - Peter's deprecation of query-migrationthreads command - Peter's cleanup/fixes from the "export misc.h" series - Maciej's two small patches from multifd+vfio series # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZyTbVRIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wan3wD+L4TVNDc34Hy4mvWu7u1lCOePX0GBdUEc # oEeBGblwbrcBAIR8d+5z9O5YcWH1coozG1aUC4qCtSHHk5TGbJk4/UUD # =XB5Q # -----END PGP SIGNATURE----- # gpg: Signature made Fri 01 Nov 2024 13:44:53 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal] # gpg: aka "Peter Xu <peterx@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-20241030-pull-request' of https://gitlab.com/peterx/qemu: migration/multifd: Zero p->flags before starting filling a packet migration/ram: Add load start trace event migration: Drop migration_is_idle() migration: Drop migration_is_setup_or_active() migration: Unexport ram_mig_init() migration: Unexport dirty_bitmap_mig_init() migration: Take migration object refcount earlier for threads migration: Deprecate query-migrationthreads command migration/dirtyrate: Silence warning about strcpy() on OpenBSD tests/migration: Add case for periodic ramblock dirty sync migration: Support periodic RAMBlock dirty bitmap sync migration: Remove "rs" parameter in migration_bitmap_sync_precopy migration: Move cpu-throttle.c from system to migration migration: Stop CPU throttling conditionally accel/tcg/icount-common: Remove the reference to the unused header file migration: Ensure vmstate_save() sets errp migration: Put thread names together with macros migration: Cleanup migrate_fd_cleanup() on accessing to_dst_file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-31accel/tcg/icount-common: Remove the reference to the unused header fileHyman Huang1-1/+0
Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/r/5e33b423d0b8506e5cb33fff42b50aa301b7731b.1729146786.git.yong.huang@smartx.com Signed-off-by: Peter Xu <peterx@redhat.com>
2024-10-31accel: remove dead statement and useless assertionPaolo Bonzini1-3/+1
ops is assigned again just below, and the result of the assignment must be non-NULL. Originally, the check for NULL was meant to be a check for the existence of the ops class: ops = ACCEL_OPS_CLASS(object_class_by_name(ops_name)); ... g_assert(ops != NULL); (where the ops assignment begot the one that I am removing); but this is meaningless now that oc is checked to be non-NULL before ops is assigned (commit 5141e9a23fc, "accel: abort if we fail to load the accelerator plugin", 2022-11-06). Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-24plugins: fix qemu_plugin_resetPierrick Bouvier1-0/+4
34e5e1 refactored the plugin context initialization. After this change, tcg_ctx->plugin_insn is not reset inconditionnally anymore, but only if one plugin at least is active. When uninstalling the last plugin active, we stopped reinitializing tcg_ctx->plugin_insn, which leads to memory callbacks being emitted. This results in an error as they don't appear in a plugin op sequence as expected. The correct fix is to make sure we reset plugin translation variables after current block translation ends. This way, we can catch any potential misuse of those after a given block, in more than fixing the current bug. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2570 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Robbin Ehn <rehn@rivosinc.com> Message-Id: <20241015003819.984601-1-pierrick.bouvier@linaro.org> [AJB: trim patch version details from commit msg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-19-alex.bennee@linaro.org>
2024-10-24accel/tcg: add tracepoints for cpu_loop_exit_atomicAlex Bennée3-1/+22
We try to avoid using cpu_loop_exit_atomic as it brings in an all-core sync point. However on some cpu/kernel/benchmark combinations it is starting to show up in the performance profile. To make it easier to see whats going on add tracepoints for the slow path so we can see what is triggering the wait. It seems for a modern CPU it can be quite a bit, for example: ./qemu-system-aarch64 \ -machine type=virt,virtualization=on,pflash0=rom,pflash1=efivars,gic-version=max \ -smp 4 \ -accel tcg \ -device virtio-net-pci,netdev=unet \ -device virtio-scsi-pci \ -device scsi-hd,drive=hd \ -netdev user,id=unet,hostfwd=tcp::2222-:22 \ -blockdev driver=raw,node-name=hd,file.driver=host_device,file.filename=/dev/zen-ssd2/trixie-arm64,discard=unmap \ -serial mon:stdio \ -blockdev node-name=rom,driver=file,filename=(pwd)/pc-bios/edk2-aarch64-code.fd,read-only=true \ -blockdev node-name=efivars,driver=file,filename=$HOME/images/qemu-arm64-efivars \ -m 8192 \ -object memory-backend-memfd,id=mem,size=8G,share=on \ -kernel /home/alex/lsrc/linux.git/builds/arm64/arch/arm64/boot/Image -append "root=/dev/sda2 console=ttyAMA0 systemd.unit=benchmark-stress-ng.service" \ -display none -d trace:load_atom\*_fallback,trace:store_atom\*_fallback With: -cpu neoverse-v1,pauth-impdef=on => 2203343 With: -cpu cortex-a76 => 0 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-9-alex.bennee@linaro.org>
2024-10-17accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vmPaolo Bonzini1-6/+6
The exact set of available memory attributes can vary by VM. In the future it might vary depending on enabled capabilities, too. Query the extension on the VM level instead of on the KVM level, and only after architecture-specific initialization. Inspired by an analogous patch by Tom Dohrmann. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-17accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vmPaolo Bonzini1-6/+6
KVM_CAP_MULTI_ADDRESS_SPACE used to be a global capability, but with the introduction of AMD SEV-SNP confidential VMs, the number of address spaces can vary by VM type. Query the extension on the VM level instead of on the KVM level. Inspired by an analogous patch by Tom Dohrmann. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-17accel/kvm: check for KVM_CAP_READONLY_MEM on VMTom Dohrmann1-1/+1
KVM_CAP_READONLY_MEM used to be a global capability, but with the introduction of AMD SEV-SNP confidential VMs, this extension is not always available on all VM types [1,2]. Query the extension on the VM level instead of on the KVM level. [1] https://patchwork.kernel.org/project/kvm/patch/20240809190319.1710470-2-seanjc@google.com/ [2] https://patchwork.kernel.org/project/kvm/patch/20240902144219.3716974-1-erbse.13@gmx.de/ Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Tom Dohrmann <erbse.13@gmx.de> Link: https://lore.kernel.org/r/20240903062953.3926498-1-erbse.13@gmx.de Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-17KVM: Rename KVMState->nr_slots to nr_slots_maxPeter Xu1-6/+6
This value used to reflect the maximum supported memslots from KVM kernel. Rename it to be clearer. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Link: https://lore.kernel.org/r/20240917163835.194664-5-peterx@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-09-26 12:36:50 +0000