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2021-07-30accel/tcg: Remove double bswap for helper_atomic_sto_*_mmuRichard Henderson1-1/+0
This crept in as either a cut-and-paste error, or rebase error. Fixes: cfec388518d ("atomic_template: add inline trace/plugin helpers") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210729004647.282017-24-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-29kvm: ppc: Print meaningful message on KVM_CREATE_VM failureFabiano Rosas1-0/+6
PowerPC has two KVM types (HV, PR) that translate into three kernel modules: kvm.ko - common kvm code kvm_hv.ko - kvm running with MSR_HV=1 or MSR_HV|PR=0 in a nested guest. kvm_pr.ko - kvm running in usermode MSR_PR=1. Since the two KVM types can both be running at the same time, this creates a situation in which it is possible for one or both of the modules to fail to initialize, leaving the generic one behind. This leads QEMU to think it can create a guest, but KVM will fail when calling the type-specific code: ioctl(KVM_CREATE_VM) failed: 22 Invalid argument qemu-kvm: failed to initialize KVM: Invalid argument Ideally this would be solved kernel-side, but it might be a while until we can get rid of one of the modules. So in the meantime this patch tries to make this less confusing for the end user by adding a more elucidative message: ioctl(KVM_CREATE_VM) failed: 22 Invalid argument PPC KVM module is not loaded. Try 'modprobe kvm_hv'. [dwg: Fixed error in #elif which failed compile on !ppc hosts] Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20210722141340.2367905-1-farosas@linux.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-07-26accel/tcg: Remove unused variable in cpu_execRichard Henderson1-8/+2
From clang-13: accel/tcg/cpu-exec.c:783:15: error: variable 'cc' set but not used \ [-Werror,-Wunused-but-set-variable] Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-26accel/tcg: Remove unnecessary check on icount_extra in cpu_loop_exec_tb()Peter Maydell1-1/+3
In cpu_loop_exec_tb(), we decide whether to look for a TB with exactly insns_left instructions in it using the condition (!cpu->icount_extra && insns_left > 0 && insns_left < tb->icount) The check for icount_extra == 0 is unnecessary, because we just set insns_left = MIN(0xffff, cpu->icount_budget); icount_extra = icount_budget - insns_left; and so icount_extra can only be non-zero if icount_budget > 0xffff and insns_left == 0xffff. But in that case insns_left >= tb->icount because 0xffff is much larger than TCG_MAX_INSNS, so the condition will be false anyway. Remove the unnecessary check, and instead assert: * that we are only going to execute a partial TB here if the icount budget has run out (ie icount_extra == 0) * that the number of insns we're going to execute does fit into the CF_COUNT_MASK Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210725174405.24568-3-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-26accel/tcg: Don't use CF_COUNT_MASK as the max value of icount_decr.u16.lowPeter Maydell1-1/+1
In cpu_loop_exec_tb() we were bounding the number of insns we might try to execute in a TB using CF_COUNT_MASK. This is incorrect, because we can validly put up to 0xffff into icount_decr.u16.low. In particular, since commit 78ff82bb1b67c0d7 reduced CF_COUNT_MASK to 511 this meant that we would incorrectly only try to execute 511 instructions in a 512-instruction TB, which could result in QEMU hanging when in icount mode. Use the actual maximum value, which is 0xffff. (This brings this code in to line with the similar logic in icount_prepare_for_run() in tcg-accel-ops-icount.c.) Fixes: 78ff82bb1b67c0d7 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/499 Message-Id: <20210725174405.24568-2-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Record singlestep_enabled in tb->cflagsRichard Henderson3-11/+7
Set CF_SINGLE_STEP when single-stepping is enabled. This avoids the need to flush all tb's when turning single-stepping on or off. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Hoist tb_cflags to a local in translator_loopRichard Henderson1-5/+4
The access internal to tb_cflags() is atomic. Avoid re-reading it as such for the multiple uses. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Move breakpoint recognition outside translationRichard Henderson2-26/+89
Trigger breakpoints before beginning translation of a TB that would begin with a BP. Thus we never generate code for the BP at all. Single-step instructions within a page containing a BP so that we are sure to check each insn for the BP as above. We no longer need to flush any TBs when changing BPs. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/286 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/404 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/489 Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Merge tb_find into its only callerRichard Henderson1-43/+42
We are going to want two things: (1) check for breakpoints will want to break out of the loop here, (2) cflags can only be calculated with pc in hand. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomicRichard Henderson1-3/+8
Request that the one TB returns immediately, so that we release the exclusive lock as soon as possible. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210717221851.2124573-7-richard.henderson@linaro.org>
2021-07-21accel/tcg: Handle -singlestep in curr_cflagsRichard Henderson3-3/+9
Exchange the test in translator_use_goto_tb for CF_NO_GOTO_TB, and the test in tb_gen_code for setting CF_COUNT_MASK to 1. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210717221851.2124573-6-richard.henderson@linaro.org>
2021-07-21accel/tcg: Drop CF_NO_GOTO_PTR from -d nochainRichard Henderson1-1/+1
The purpose of suppressing goto_ptr from -d nochain had been to return to the main loop so that -d cpu would be recognized. But we now include -d cpu logging in helper_lookup_tb_ptr so there is no need to exclude goto_ptr. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210717221851.2124573-5-richard.henderson@linaro.org>
2021-07-21accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTRRichard Henderson2-1/+12
Move the -d nochain check to bits on tb->cflags. These will be used for more than -d nochain shortly. Set bits during curr_cflags, test them in translator_use_goto_tb, assert we're not doing anything odd in tcg_gen_goto_tb. The test in tcg_gen_exit_tb is redundant with the assert for goto_tb_issue_mask. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210717221851.2124573-4-richard.henderson@linaro.org>
2021-07-21accel/tcg: Move curr_cflags into cpu-exec.cRichard Henderson1-0/+5
We will shortly have more than a simple member read here, with stuff not necessarily exposed to exec/exec-all.h. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210717221851.2124573-3-richard.henderson@linaro.org>
2021-07-21accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNSRichard Henderson1-3/+2
The space reserved for CF_COUNT_MASK was overly large. Reduce to free up cflags bits and eliminate an extra test. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210717221851.2124573-2-richard.henderson@linaro.org>
2021-07-21accel/tcg: Push trace info building into atomic_common.c.incRichard Henderson2-48/+37
Use trace_mem_get_info instead of trace_mem_build_info, using the TCGMemOpIdx that we already have. Do this in the atomic_trace_*_pre function as common subroutines. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Expand ATOMIC_MMU_LOOKUP_*Richard Henderson3-24/+36
Unify the parameters of atomic_mmu_lookup between cputlb.c and user-exec.c. Call the function directly, and remove the macros. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Remove ATOMIC_MMU_DECLSRichard Henderson3-14/+0
All definitions are now empty. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Fold EXTRA_ARGS into atomic_template.hRichard Henderson3-18/+20
All instances of EXTRA_ARGS are now identical. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Standardize atomic helpers on softmmu apiRichard Henderson4-104/+70
Reduce the amount of code duplication by always passing the TCGMemOpIdx argument to helper_atomic_*. This is not currently used for user-only, but it's easy to ignore. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson2-20/+39
Always provide the atomic interface using TCGMemOpIdx oi and uintptr_t retaddr. Rename from helper_* to cpu_* so as to (mostly) match the exec/cpu_ldst.h functions, and to emphasize that they are not callable from TCG directly. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21qemu/atomic: Add aligned_{int64,uint64}_t typesRichard Henderson1-2/+2
Use it to avoid some clang-12 -Watomic-alignment errors, forcing some structures to be aligned and as a pointer when we have ensured that the address is aligned. Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-14plugins: fix-up handling of internal hostaddr for 32 bitAlex Bennée1-1/+1
The compiler rightly complains when we build on 32 bit that casting uint64_t into a void is a bad idea. We are really dealing with a host pointer at this point so treat it as such. This does involve a uintptr_t cast of the result of the TLB addend as we know that has to point to the host memory. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210709143005.1554-28-alex.bennee@linaro.org>
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' ↵Peter Maydell6-105/+113
into staging Add translator_use_goto_tb. Cleanups in prep of breakpoint fixes. Misc fixes. # gpg: Signature made Sat 10 Jul 2021 16:29:14 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210710: (41 commits) cpu: Add breakpoint tracepoints tcg: Remove TCG_TARGET_HAS_goto_ptr accel/tcg: Log tb->cflags with -d exec accel/tcg: Split out log_cpu_exec accel/tcg: Move tb_lookup to cpu-exec.c accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.c target/i386: Use cpu_breakpoint_test in breakpoint_handler tcg: Fix prologue disassembly target/xtensa: Use translator_use_goto_tb target/tricore: Use tcg_gen_lookup_and_goto_ptr target/tricore: Use translator_use_goto_tb target/sparc: Use translator_use_goto_tb target/sh4: Use translator_use_goto_tb target/s390x: Remove use_exit_tb target/s390x: Use translator_use_goto_tb target/rx: Use translator_use_goto_tb target/riscv: Use translator_use_goto_tb target/ppc: Use translator_use_goto_tb target/openrisc: Use translator_use_goto_tb target/nios2: Use translator_use_goto_tb ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-09accel/tcg: Log tb->cflags with -d execRichard Henderson1-3/+3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Split out log_cpu_execRichard Henderson1-27/+34
Split out CPU_LOG_EXEC and CPU_LOG_TB_CPU logging from cpu_tb_exec to a new function. Perform only one pc range check after a combined mask check. Use the new function in lookup_tb_ptr. This enables CPU_LOG_TB_CPU between indirectly chained tbs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Move tb_lookup to cpu-exec.cRichard Henderson2-50/+30
Now that we've moved helper_lookup_tb_ptr, the only user of tb-lookup.h is cpu-exec.c; merge the contents in. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.cRichard Henderson2-22/+30
This will allow additional code sharing. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Introduce translator_use_goto_tbRichard Henderson1-0/+11
Add a generic version of the common use_goto_tb test. Various targets avoid the page crossing test for CONFIG_USER_ONLY, but that is wrong: mmap and mprotect can change page permissions. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Move tb_phys_invalidate_count to tb_ctxRichard Henderson2-4/+5
We can call do_tb_phys_invalidate from an iocontext, which has no per-thread tcg_ctx. Move this to tb_ctx, which is global. The actual update still takes place with a lock held, so only an atomic set is required, not an atomic increment. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/457 Tested-by: Viktor Ashirov <vashirov@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Bake tb_destroy() into tcg_region_treeLiren Wei1-6/+0
The function is called only at tcg_gen_code() when duplicated TBs are translated by different threads, and when the tcg_region_tree is reset. Bake it into the underlying GTree as its value destroy function to unite these situations. Also remove tcg_region_tree_traverse() which now becomes useless. Signed-off-by: Liren Wei <lrwei@bupt.edu.cn> Message-Id: <8dc352f08d038c4e7a1f5f56962398cdc700c3aa.1625404483.git.lrwei@bupt.edu.cn> [rth: Name the new tb_tc_cmp parameter correctly.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09accel/tcg: Hoist tcg_tb_insert() up above tb_link_page()Liren Wei1-1/+8
TranslationBlocks not inserted into the corresponding region tree shall be regarded as partially initialized objects, and needs to be finalized first before inserting into QHT. Signed-off-by: Liren Wei <lrwei@bupt.edu.cn> Message-Id: <f9fc263f71e11b6308d8c1fbc0dd366bf4aeb532.1625404483.git.lrwei@bupt.edu.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09monitor/tcg: move tcg hmp commands to accel/tcg, register them dynamicallyGerd Hoffmann2-0/+30
One more little step towards modular tcg ... Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Jose R. Ziviani <jziviani@suse.de> Message-Id: <20210624103836.2382472-35-kraxel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09accel: build tcg modularGerd Hoffmann1-1/+4
Build tcg accel ops as module. Which is only a small fraction of tcg. Also only x86 for now. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jose R. Ziviani <jziviani@suse.de> Message-Id: <20210624103836.2382472-30-kraxel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09accel: add tcg module annotationsGerd Hoffmann2-0/+2
Add module annotations for tcg so autoloading works. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jose R. Ziviani <jziviani@suse.de> Message-Id: <20210624103836.2382472-29-kraxel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09accel: build qtest modularGerd Hoffmann1-6/+2
Allow building accelerators as module. Start with qtest as first user. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jose R. Ziviani <jziviani@suse.de> Message-Id: <20210624103836.2382472-28-kraxel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09accel: add qtest module annotationsGerd Hoffmann1-0/+2
Add module annotations for qtest so autoloading works. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jose R. Ziviani <jziviani@suse.de> Message-Id: <20210624103836.2382472-27-kraxel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-09accel: autoload modulesGerd Hoffmann2-2/+2
Call module_object_class_by_name() instead of object_class_by_name() for objects possibly implemented as module Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jose R. Ziviani <jziviani@suse.de> Message-Id: <20210624103836.2382472-26-kraxel@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-29tcg: Use correct trap number for page faults on *BSD systemsWarner Losh1-2/+18
The trap number for a page fault on BSD systems is T_PAGEFLT not 0xe -- 0xe is used by Linux and represents the intel hardware trap vector. The BSD kernels, however, translate this to T_PAGEFLT in their Xpage, Xtrap0e, Xtrap14, etc fault handlers. This is true for i386 and x86_64, though the name of the trap hanlder can very on the flavor of BSD. As far as I can tell, Linux doesn't provide a define for this value. Invent a new one (PAGE_FAULT_TRAP) and use it instead to avoid uglier ifdefs. Signed-off-by: Mark Johnston <markj@FreeBSD.org> Signed-off-by: Juergen Lock <nox@FreeBSD.org> [ Rework to avoid ifdefs and expand it to i386 ] Signed-off-by: Warner Losh <imp@bsdimp.com> Message-Id: <20210625045707.84534-3-imp@bsdimp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-25KVM: Fix dirty ring mmap incorrect size due to renaming accidentPeter Xu1-2/+2
Found this when I wanted to try the per-vcpu dirty rate series out, then I found that it's not really working and it can quickly hang death a guest. I found strange errors (e.g. guest crash after migration) happens even without the per-vcpu dirty rate series. When merging dirty ring, probably no one notice that the trivial renaming diff [1] missed two existing references of kvm_dirty_ring_sizes; they do matter since otherwise we'll mmap() a shorter range of memory after the renaming. I think it didn't SIGBUS for me easily simply because some other stuff within qemu mmap()ed right after the dirty rings (e.g. when testing 4096 slots, it aligned with one small page on x86), so when we access the rings we've been reading/writting to random memory elsewhere of qemu. Fix the two sizes when map/unmap the shared dirty gfn memory. [1] https://lore.kernel.org/qemu-devel/dac5f0c6-1bca-3daf-e5d2-6451dbbaca93@redhat.com/ Cc: Hyman Huang <huangy81@chinatelecom.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210609014355.217110-1-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-19accel/tcg: Probe the proper permissions for atomic opsRichard Henderson3-44/+83
We had a single ATOMIC_MMU_LOOKUP macro that probed for read+write on all atomic ops. This is incorrect for plain atomic load and atomic store. For user-only, we rely on the host page permissions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/390 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19accel/tcg: Add tcg call flags to plugins helpersRichard Henderson1-2/+2
As noted by qemu-plugins.h, plugins can neither read nor write guest registers. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19plugins: Drop tcg_flags from struct qemu_plugin_dyn_cbRichard Henderson2-5/+4
As noted by qemu-plugins.h, enum qemu_plugin_cb_flags is currently unused -- plugins can neither read nor write guest registers. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19accel/tcg/plugin-gen: Drop inline markersRichard Henderson1-7/+5
Let the compiler decide on inlining. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-13tcg: Move tcg_init_ctx and tcg_ctx from accel/tcg/Richard Henderson1-3/+0
These variables belong to the jit side, not the user side. Since tcg_init_ctx is no longer used outside of tcg/, move the declaration to tcg-internal.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11accel/tcg: Pass down max_cpus to tcg_initRichard Henderson1-1/+9
Start removing the include of hw/boards.h from tcg/. Pass down the max_cpus value from tcg_init_machine, where we have the MachineState already. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11accel/tcg: Use MiB in tcg_init_machineRichard Henderson1-1/+2
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11accel/tcg: Merge tcg_exec_init into tcg_init_machineRichard Henderson3-20/+19
There is only one caller, and shortly we will need access to the MachineState, which tcg_init_machine already has. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11tcg: Create tcg_initRichard Henderson1-2/+1
Perform both tcg_context_init and tcg_region_init. Do not leave this split to the caller. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-11accel/tcg: Rename tcg_init to tcg_init_machineRichard Henderson1-2/+2
We shortly want to use tcg_init for something else. Since the hook is called init_machine, match that. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-08-24 10:44:59 +0000