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2019-02-11cputlb: update TLB entry/index after tlb_fillEmilio G. Cota2-0/+12
2019-02-07Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190206' into stagingPeter Maydell1-3/+0
2019-02-06accel/tcg: Consider cluster index in tb_lookup__cpu_state()Peter Maydell1-3/+0
2019-02-05cpu-exec: reset BQL after longjmp in cpu_exec_step_atomicEmilio G. Cota1-0/+3
2019-02-05cpu-exec: add assert_no_pages_locked() after longjmpEmilio G. Cota1-0/+1
2019-01-30tcg: Fix LGPL version numberThomas Huth9-9/+9
2019-01-29accel/tcg: Add cluster number to TCG TB hashPeter Maydell2-0/+6
2019-01-29accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs writePeter Maydell1-14/+52
2019-01-28cputlb: Remove static tlb sizingRichard Henderson1-21/+0
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota1-5/+197
2019-01-28cputlb: do not evict empty entries to the vtlbEmilio G. Cota1-1/+10
2019-01-28tcg: Add opcodes for vector minmax arithmeticRichard Henderson2-0/+244
2019-01-28tcg: Add gvec expanders for nand, nor, eqvRichard Henderson2-0/+36
2019-01-11build-sys: don't include windows.h, osdep.h does itMarc-André Lureau1-4/+0
2018-12-26tcg: Add RISC-V cpu signal handlerAlistair Francis1-0/+75
2018-10-31cputlb: Remove tlb_c.pending_flushesRichard Henderson1-14/+2
2018-10-31cputlb: Filter flushes on already clean tlbsRichard Henderson1-10/+25
2018-10-31cputlb: Count "partial" and "elided" tlb flushesRichard Henderson2-7/+19
2018-10-31cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidxRichard Henderson1-46/+12
2018-10-31cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_workRichard Henderson1-72/+21
2018-10-31cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson1-3/+2
2018-10-31cputlb: Split large page tracking per mmu_idxRichard Henderson1-77/+61
2018-10-31cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson1-12/+23
2018-10-31cputlb: Remove tcg_enabled hack from tlb_flush_nocheckRichard Henderson1-7/+0
2018-10-31cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson1-24/+24
2018-10-18cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota2-12/+19
2018-10-18tcg: Split CONFIG_ATOMIC128Richard Henderson3-7/+21
2018-10-18tcg: Add tlb_index and tlb_entry helpersRichard Henderson2-63/+61
2018-10-18cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota1-71/+84
2018-10-18cputlb: fix assert_cpu_is_self macroEmilio G. Cota1-2/+2
2018-10-18exec: introduce tlb_initEmilio G. Cota1-0/+4
2018-10-18tcg: access cpu->icount_decr.u16.high with atomicsEmilio G. Cota2-2/+2
2018-10-18tcg: Implement CPU_LOG_TB_NOCHAIN during expansionRichard Henderson1-1/+1
2018-10-02accel/tcg: Remove dead codeThomas Huth1-9/+0
2018-10-02translator: fix breakpoint processingPavel Dovgalyuk1-2/+6
2018-09-26qht: drop ht argument from qht iteratorsEmilio G. Cota1-4/+2
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell1-21/+8
2018-08-14accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code()Peter Maydell1-85/+10
2018-08-14accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAMPeter Maydell1-1/+18
2018-08-14accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint()Peter Maydell1-1/+3
2018-08-14accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookupsPeter Maydell1-0/+3
2018-08-14accel/tcg: Pass read access type through to io_readx()Peter Maydell2-6/+10
2018-07-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-1/+1
2018-07-16accel/tcg: Assert that tlb fill gave us a valid TLB entryPeter Maydell1-2/+2
2018-07-16accel/tcg: Use correct test when looking in victim TLB for codePeter Maydell1-1/+1
2018-07-16accel: Fix typo and grammar in commentStefan Weil1-1/+1
2018-07-09translate-all: honour CF_NOCACHE in tb_gen_codeEmilio G. Cota1-15/+19
2018-07-02accel/tcg: Avoid caching overwritten tlb entriesRichard Henderson1-26/+35
2018-07-02accel/tcg: Don't treat invalid TLB entries as needing recheckPeter Maydell1-1/+2
2018-07-02accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()Peter Maydell1-2/+1
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