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path: root/accel/tcg/cputlb.c
AgeCommit message (Expand)AuthorFilesLines
2018-07-02accel/tcg: Avoid caching overwritten tlb entriesRichard Henderson1-26/+35
2018-07-02accel/tcg: Don't treat invalid TLB entries as needing recheckPeter Maydell1-1/+2
2018-07-02accel/tcg: Correct "is this a TLB miss" check in get_page_addr_code()Peter Maydell1-2/+1
2018-07-02tcg: Define and use new tlb_hit() and tlb_hit_page() functionsPeter Maydell1-10/+5
2018-06-26tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZEPeter Maydell1-20/+109
2018-06-15cputlb: remove tb_lock from tlb_flush functionsEmilio G. Cota1-8/+0
2018-06-15exec.c: Handle IOMMUs in address_space_translate_for_iotlb()Peter Maydell1-1/+2
2018-06-15cputlb: Pass cpu_transaction_failed() the correct physaddrPeter Maydell1-13/+31
2018-06-15cpu-defs.h: Document CPUIOTLBEntry 'addr' fieldPeter Maydell1-0/+12
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier1-5/+8
2017-11-21accel/tcg: Handle atomic accesses to notdirty memory correctlyPeter Maydell1-13/+25
2017-11-15tcg: Record code_gen_buffer address for user-only memory helpersRichard Henderson1-0/+1
2017-10-20accel/tcg: allow to invalidate a write TLB entry immediatelyDavid Hildenbrand1-1/+4
2017-10-10cputlb: bring back tlb_flush_count under !TLB_DEBUGEmilio G. Cota1-3/+14
2017-09-25accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)Alex Bennée1-2/+2
2017-09-04cputlb: Support generating CPU exceptions on memory transaction failuresPeter Maydell1-2/+30
2017-06-30tcg: consistently access cpu->tb_jmp_cache atomicallyEmilio G. Cota1-2/+2
2017-06-27exec: allow to get a pointer for some mmio memory regionKONRAD Frederic1-0/+10
2017-06-27cputlb: fix the way get_page_addr_code fills the tlbKONRAD Frederic1-2/+4
2017-06-27cputlb: move get_page_addr_codeKONRAD Frederic1-35/+35
2017-06-27cputlb: cleanup get_page_addr_code to use VICTIM_TLB_HITKONRAD Frederic1-9/+9
2017-06-15tcg: move tcg related files into accel/tcg/ subdirectoryYang Zhong1-0/+1051