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2024-12-31MAINTAINERS: Add myself as maintainer for apple-gfx, reviewer for HVFPhil Dennis-Jordan1-0/+7
I'm happy to take responsibility for the macOS PV graphics code. As HVF patches don't seem to get much attention at the moment, I'm also adding myself as designated reviewer for HVF and x86 HVF to try and improve that. Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Roman Bolshakov <rbolshakov@ddn.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241223221645.29911-6-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-22Merge tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu into ↵Stefan Hajnoczi1-0/+5
staging Hi, "Host Memory Backends" and "Memory devices" queue ("mem"): - Fixup handling of virtio-mem unplug during system resets, as preparation for s390x support (especially kdump in the Linux guest) - virtio-mem support for s390x # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEG9nKrXNcTDpGDfzKTd4Q9wD/g1oFAmdnFD4RHGRhdmlkQHJl # ZGhhdC5jb20ACgkQTd4Q9wD/g1rWBBAAp7WkYaNAjRy1PgpjNZ3z1gUJc/vk+skJ # xVgGodA8txrJOFpNrbTyfhrdLs2TV4oWDvB/zrZRRtuxvur3O1EhFd9k6EqXuydr # 0FunvLvVJwRHfEZycjN4aacQMRH3CJw07OaTzexeSl5UR/6w5PRofwUK4HX7W/Ka # arqomGa3OJrs1+WgkV0Qcn4vh9HLRVv3iNC2Xo4W1wOCr1Du9zSPn9oC7zOQ0EO4 # ZC//7QsdkNRjUX/yMXMkhlSXx3b/RmRg2DBrxo7BZXg27VwGu4uHxL4LRBZiB2A7 # V9MqFOcVKzPMkXKTRjrgZ0vXQx1MPJ6WprEihMzMpYU6DrpA7KN/l8Ca8H24B2ln # h7+bmkDsHVVcWovE9ii/9cMRfws6uWXXg3KoA8RQ8IbX1tU02lblw2uHhXEzcoge # npqp/Z5LAiKVMetEnNnLH5thjut5PAEjuqD00cmZAMy4DNngLX2bGSdzMeVBkDMa # 78ehLGRplm3t7ibUfaZaMKe6UD9tFrcD6XKsvUTXXHNbYO8ynbx58WOxSZmY98zU # n3JNQRqtXYjBVlH3Dqm47vOTZHgOzFv3raa8BmSLpcBDeTXCTcUIl20s77dGw/vT # r5YNCMN7O4YPFKUoRK9604QTgw6qlYaRTQlJD09usprGqVylb6gQtfZZuZkYDMp8 # sEI77QHsePA= # =HDxr # -----END PGP SIGNATURE----- # gpg: Signature made Sat 21 Dec 2024 14:17:18 EST # gpg: using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A # gpg: issuer "david@redhat.com" # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [unknown] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] # gpg: aka "David Hildenbrand <hildenbr@in.tum.de>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 1BD9 CAAD 735C 4C3A 460D FCCA 4DDE 10F7 00FF 835A * tag 'mem-2024-12-21' of https://github.com/davidhildenbrand/qemu: s390x: virtio-mem support s390x/virtio-ccw: add support for virtio based memory devices s390x: remember the maximum page size s390x/pv: prepare for memory devices s390x/s390-virtio-ccw: prepare for memory devices s390x/s390-skeys: prepare for memory devices s390x/s390-stattrib-kvm: prepare for memory devices and sparse memory layouts s390x/s390-hypercall: introduce DIAG500 STORAGE_LIMIT s390x: introduce s390_get_memory_limit() s390x/s390-virtio-ccw: move setting the maximum guest size from sclp to machine code s390x: rename s390-virtio-hcall* to s390-hypercall* s390x/s390-virtio-hcall: prepare for more diag500 hypercalls s390x/s390-virtio-hcall: remove hypercall registration mechanism s390x/s390-virtio-ccw: don't crash on weird RAM sizes virtio-mem: unplug memory only during system resets, not device resets Conflicts: - hw/s390x/s390-stattrib-kvm.c sysemu/ -> system/ header rename conflict. - hw/s390x/virtio-ccw-mem.c Make Property array const and removed DEFINE_PROP_END_OF_LIST() to conform to the latest conventions. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21s390x: virtio-mem supportDavid Hildenbrand1-0/+2
Let's add our virtio-mem-ccw proxy device and wire it up. We should be supporting everything (e.g., device unplug, "dynamic-memslots") that we already support for the virtio-pci variant. With a Linux guest that supports virtio-mem (and has automatic memory onlining properly configured) the following example will work: 1. Start a VM with 4G initial memory and a virtio-mem device with a maximum capacity of 16GB: qemu/build/qemu-system-s390x \ --enable-kvm \ -m 4G,maxmem=20G \ -nographic \ -smp 8 \ -hda Fedora-Server-KVM-40-1.14.s390x.qcow2 \ -chardev socket,id=monitor,path=/var/tmp/monitor,server,nowait \ -mon chardev=monitor,mode=readline \ -object memory-backend-ram,id=mem0,size=16G,reserve=off \ -device virtio-mem-ccw,id=vmem0,memdev=mem0,dynamic-memslots=on 2. Query the current size of virtio-mem device: (qemu) info memory-devices Memory device [virtio-mem]: "vmem0" memaddr: 0x100000000 node: 0 requested-size: 0 size: 0 max-size: 17179869184 block-size: 1048576 memdev: /objects/mem0 3. Request to grow it to 8GB (hotplug 8GB): (qemu) qom-set vmem0 requested-size 8G (qemu) info memory-devices Memory device [virtio-mem]: "vmem0" memaddr: 0x100000000 node: 0 requested-size: 8589934592 size: 8589934592 max-size: 17179869184 block-size: 1048576 memdev: /objects/mem0 4. Request to grow to 16GB (hotplug another 8GB): (qemu) qom-set vmem0 requested-size 16G (qemu) info memory-devices Memory device [virtio-mem]: "vmem0" memaddr: 0x100000000 node: 0 requested-size: 17179869184 size: 17179869184 max-size: 17179869184 block-size: 1048576 memdev: /objects/mem0 5. Try to hotunplug all memory again, shrinking to 0GB: (qemu) qom-set vmem0 requested-size 0G (qemu) info memory-devices Memory device [virtio-mem]: "vmem0" memaddr: 0x100000000 node: 0 requested-size: 0 size: 0 max-size: 17179869184 block-size: 1048576 memdev: /objects/mem0 6. If it worked, unplug the device (qemu) device_del vmem0 (qemu) info memory-devices (qemu) object_del mem0 7. Hotplug a new device with a smaller capacity and directly size it to 1GB (qemu) object_add memory-backend-ram,id=mem0,size=8G,reserve=off (qemu) device_add virtio-mem-ccw,id=vmem0,memdev=mem0,\ dynamic-memslots=on,requested-size=1G (qemu) info memory-devices Memory device [virtio-mem]: "vmem0" memaddr: 0x100000000 node: 0 requested-size: 1073741824 size: 1073741824 max-size: 8589934592 block-size: 1048576 memdev: /objects/mem0 Trying to use a virtio-mem device backed by hugetlb into a !hugetlb VM correctly results in the error: ... Memory device uses a bigger page size than initial memory Note that the virtio-mem driver in Linux will supports 1 MiB (pageblock) granularity. Message-ID: <20241219144115.2820241-15-david@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi1-38/+38
Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21s390x/virtio-ccw: add support for virtio based memory devicesDavid Hildenbrand1-0/+3
Let's implement support for abstract virtio based memory devices, using the virtio-pci implementation as an orientation. Wire them up in the machine hotplug handler, taking care of s390x page size limitations. As we neither support virtio-mem or virtio-pmem yet, the code is effectively unused. We'll implement support for virtio-mem based on this next. Note that we won't wire up the virtio-pci variant (should currently be impossible due to lack of support for MSI-X), but we'll add a safety net to reject plugging them in the pre-plug handler. Message-ID: <20241219144115.2820241-14-david@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé1-38/+38
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-12-20MAINTAINERS: Cover RISC-V HTIF interfacePhilippe Mathieu-Daudé1-0/+2
The HTIF interface is RISC-V specific, add it within the MAINTAINERS section covering hw/riscv/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241129154304.34946-2-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-20hw/riscv: Add Microblaze V generic boardSai Pavan Boddu1-0/+6
Add a basic board with interrupt controller (intc), timer, serial (uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000 (configured via command line eg. -m 2g). This is basic configuration which matches HW generated out of AMD Vivado (design tools). But initial configuration is going beyond what it is configured by default because validation should be done on other configurations too. That's why wire also additional uart16500, axi ethernet(with axi dma). GPIOs, i2c and qspi is also listed for completeness. IRQ map is: (addr) 0 - timer (0x41c00000) 1 - uartlite (0x40600000) 2 - i2c (0x40800000) 3 - qspi (0x44a00000) 4 - uart16550 (0x44a10000) 5 - emaclite (0x40e00000) 6 - timer2 (0x41c10000) 7 - axi emac (0x40c00000) 8 - axi dma (0x41e00000) 9 - axi dma 10 - gpio (0x40000000) 11 - gpio2 (0x40010000) 12 - gpio3 (0x40020000) Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-17tests/functional: Convert the intel_iommu avocado testThomas Huth1-0/+1
Convert the intel_iommu test to the new functional framework. This test needs some changes since we neither support the old 'LinuxTest' class in the functional framework yet, nor a way to use SSH for running commands in the guest. So we now directly download a Fedora kernel and initrd and set up the serial console for executing the commands and for looking for the results. Instead of configuring the cloud image via cloud-init, we now simply mount the file system manually from an initrd rescue shell. While the old test was exercising the network with a "dnf install" command (which is not the best option for the CI since this depends on third party servers), the new code is now setting up a little HTTP server in the guest and transfers a file from the guest to the host instead. The test should now run much faster and more reliable (since we don't depend on the third party servers for "dnf install" anymore), so we can also drop the @skipUnless decorator now. Message-ID: <20241217121550.141072-3-thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-17tests/functional: Convert the quanta-gsj avocado testThomas Huth1-0/+1
Straight forward conversion, basically just the hashsums needed to be updated to sha256 now. Message-ID: <20241206102358.1186644-6-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-17MAINTAINERS: add myself as reviewer for functional test suiteDaniel P. Berrangé1-0/+1
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20241217155953.3950506-33-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-13MAINTAINERS: correct my email addressBrian Cain1-1/+1
Mea culpa, I don't know how I got this wrong in 2dfe93699c. Still getting used to the new address, I suppose. Somehow I got it right in the mailmap, though. Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com> Message-id: 20241209181242.1434231-1-brian.cain@oss.qualcomm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-12Merge tag 'qtest-20241212-pull-request' of https://gitlab.com/farosas/qemu ↵Stefan Hajnoczi1-2/+3
into staging Qtest pull request - TIMEOUT_MULTIPLIER setting to allow tests to take longer when asan is enabled - New qtest_system_reset() wrapper to properly wait for a system reset - Split of migration-test.c into multiple files under qtest/migration/ # -----BEGIN PGP SIGNATURE----- # # iQJEBAABCAAuFiEEqhtIsKIjJqWkw2TPx5jcdBvsMZ0FAmda+84QHGZhcm9zYXNA # c3VzZS5kZQAKCRDHmNx0G+wxnXWZEACcxW/P9EiLxIeCf4ke7/qq+8HSOOLdQrEa # hP5ZCzLlY0K8KQ9fhTGvc6UgRBsScXcLuj4eoR8Gke9e4tID39XVdkion/x6OCiv # grC2Ll9/BNrWtR8DiXs3krsU1CXhav6qcT56bMiXV3Qo+KsTmB7RkpXpbkZLZxkn # P2aqZlYFS0zZ3PZQceCasQEzB6Dls7o1wNXvgSJXr2E4IuIEcbyWtQpr5DfctnfN # STbqGTgMXADyjlqh3CWwSLsZQvIVoN9+3twOrZn4j0D+fyEsTjKsZPlUpRtr72ap # FVT+zVIUfxieBlDTsRSwcieD1ePFUUjl7ikQFwypGs33TI9VDTsB88IG7h0/080o # 7dYbSMSG0pGEq9QIB8jkV26OZi3y00L/zmLMNDsN6nxKN4mSySlfVD/B/Jb70Smy # lwbLklnr921kqsF89Bsq8YRyg8bbGXtx2ifGROgqF+JtrxRW0ElF9K/h4HQtPjuD # nZJ4rtrDIv1iMTLJwbNu39fhxvuQowdBYTrbPMgw+xIv++LodqYJSDxbEX+FaDqI # LMf772jiAgesl7qe1d9TJizhvonyi9PIdcUILg0SH0H1KvoSjpS3mlGgvo8zgvh+ # zvhhzkFGDIHmlCvOaIYyCpadJ5SMMS627q/Q13X3DHjUTkpPUhxGgc9oO7T39+iA # 4dOLDRjUcg== # =H6xv # -----END PGP SIGNATURE----- # gpg: Signature made Thu 12 Dec 2024 10:05:50 EST # gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D # gpg: issuer "farosas@suse.de" # gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown] # gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D * tag 'qtest-20241212-pull-request' of https://gitlab.com/farosas/qemu: (22 commits) tests/qtest/migration: Split validation tests + misc tests/qtest/migration-test: Fix and enable test_ignore_shared tests/qtest/migration: Split CPR tests tests/qtest/migration: Split precopy tests tests/qtest/migration: Split file tests tests/qtest/migration: Split postcopy tests tests/qtest/migration: Split compression tests from migration-test.c tests/qtest/migration: Split TLS tests from migration-test.c tests/qtest/migration: Move common test code tests/qtest/migration: Isolate test initialization tests/qtest/migration: Move kvm_dirty_ring_supported to utils tests/qtest/migration: Move ufd_version_check to utils tests/qtest/migration: Rename migration-helpers.c tests/qtest/migration: Move qmp helpers to a separate file tests/qtest/migration: Move bootfile code to its own file tests/migration: Disambiguate guestperf vs. a-b tests/qtest/migration: Stop calling everything "test" tests/qtest/migration: Standardize hook names tests/qtest: Use qtest_system_reset_nowait() where appropriate tests/qtest: Use qtest_system_reset() instead of open-coded versions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12Merge tag 'pull-target-arm-20241211' of ↵Stefan Hajnoczi1-1/+3
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs * fpu: Make muladd NaN handling runtime-selected, not compile-time * fpu: Make default NaN pattern runtime-selected, not compile-time * fpu: Minor NaN-related cleanups * MAINTAINERS: email address updates # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmdZu14ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mgiD/98Q+m7/t54FdCd2bx1cr2k # dw+7DYhp+60Vo3OjlGtKWwPD67oN8e0jhOoArmJNW0Fmkcsvfvd4wv6kCf8zftLm # 0/lPO687mvFNCAprTch+z2pGB7aS0HdIr126ytsyg5PlHtldd+OBA+yUUYafR3zo # BECRSWZmMFxfl9uckJzntdntghTX5pnJDSGBYE9NEyRfo0Ntj1HvhaHSQJkqpf5B # QwE8R965CXc4i34PqlOCju47AXwJc3x36ftdiNmpPvMS4odG9yb/OmhHSgVZlThb # 1x0HEX69KF5FQbtVNDMmFyYehDzqYFpqOSa1IKtaNLmDSZJ5P8fWw4eBdMdr/QyD # QKssgHAO6Z13MLppK4B1PFtSVlsLYUURYddYUFz4RUNOxrS/pzAIT0KhClYFytQo # x9xid4fng1PY9doYEM3v4vEQCU6S+2aj2gU4EOwdB8GmMhtjSl8YlcEs7cysqkoQ # gbGX97i6Eh616q9VsRzUwcY6u4XP/lssn6I98k4AEqgRpyFCMTLyFodV89d6J4EJ # IJKsJf10gctpe1JdMgtDxuleKOZc+O5nOMJLKYwc9siakCBZsH7zmgS6m8QVoUSD # 7R+4OtbaQwM0+GPbc0AhAlDtq3Q1QAtCYa94iICUixC4NjzfdC9B9yCz1XnA7sfS # jPHU8INw6rz3psEnlFQdhA== # =+ELh # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 11:18:38 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm: (72 commits) MAINTAINERS: Add correct email address for Vikram Garhwal MAINTAINERS: update email address for Leif Lindholm softfloat: Replace WHICH with RET in parts_pick_nan softfloat: Sink frac_cmp in parts_pick_nan until needed softfloat: Share code between parts_pick_nan cases softfloat: Inline pickNaN softfloat: Use parts_pick_nan in propagateFloatx80NaN softfloat: Move propagateFloatx80NaN to softfloat.c softfloat: Pad array size in pick_nan_muladd softfloat: Remove which from parts_pick_nan_muladd softfloat: Use goto for default nan case in pick_nan_muladd softfloat: Inline pickNaNMulAdd fpu: Remove default handling for dnan_pattern target/tricore: Set default NaN pattern explicitly target/riscv: Set default NaN pattern explicitly target/hexagon: Set default NaN pattern explicitly target/xtensa: Set default NaN pattern explicitly target/sparc: Set default NaN pattern explicitly target/s390x: Set default NaN pattern explicitly target/rx: Set default NaN pattern explicitly ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12tests/migration: Disambiguate guestperf vs. a-bFabiano Rosas1-2/+3
The current build structure for migration tests is confusing. There is the tests/migration directory, which contains two different guest code implementations, one for the qtests (a-b-{bootblock|kernel}.S) and another for the guestperf script (stress.c). One uses a Makefile, while the other uses meson. The next patches will add a new qtests/migration/ directory to hold qtest code which will make the situation even more confusing. Move the guest code used by qtests into a new qtests/migration/ directory and rename the old one to tests/migration-stress. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Fabiano Rosas <farosas@suse.de>
2024-12-11MAINTAINERS: Add correct email address for Vikram GarhwalVikram Garhwal1-0/+2
Previously, maintainer role was paused due to inactive email id. Commit id: c009d715721861984c4987bcc78b7ee183e86d75. Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-11MAINTAINERS: update email address for Leif LindholmLeif Lindholm1-1/+1
I'm migrating to Qualcomm's new open source email infrastructure, so update my email address, and update the mailmap to match. Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-11tests/functional: Convert the cubieboard avocado testsThomas Huth1-0/+1
Straight forward conversion, just the hashsums needed to be updated to sha256 now. These were the last tests that used image_pow2ceil_expand in boot_linux_console.py, so we can remove that function from that file now, too. Message-ID: <20241206102358.1186644-5-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11tests/functional: Convert the smdkc210 avocado testThomas Huth1-0/+1
A straight forward conversion, just the hashsums needed to be updated to sha256 now. Message-ID: <20241206102358.1186644-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11tests/functional: Convert the emcraft_sf2 avocado testThomas Huth1-0/+1
A pretty straight-forward conversion of the emcraft_sf2 boot test to the functional framework. This was the last test that used file_truncate() in boot_linux_console.py, so we can remove that function from that file now, too. Message-ID: <20241206102358.1186644-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11tests/functional: Convert the xlnx_versal_virt avocado testThomas Huth1-0/+1
A straight-forward conversion of the xlnx_versal_virt boot test to the functional framework. Message-ID: <20241206102358.1186644-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11MAINTAINERS: Cover the tests/functional/test_sh4eb_r2d.py fileThomas Huth1-1/+1
This file should belong to the R2D machine in the MAINTAINERS file. Message-ID: <20241204071120.663446-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-03tests/qtest: drop 'fuzz-' prefix from virtio-balloon testDaniel P. Berrangé1-0/+1
This test file is expected to be extended for arbitrary virtio-balloon related tests, not merely those discovered by fuzzing. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20241129135507.699030-3-berrange@redhat.com> [PMD: Update MAINTAINERS] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com>
2024-12-03MAINTAINERS: update email addr for Brian CainBrian Cain1-1/+1
Also: add mapping for "quic_bcain@quicinc.com" which was ~briefly used for some replies to mailing list traffic. Signed-off-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241123164641.364748-2-bcain@quicinc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-03MAINTAINERS: add myself as the maintainer for LoongArch VirtMachineBibo Mao1-0/+1
Song Gao is will be sick leave for a long time, I apply for maintainer for LoongArch Virt Machine during this period, LoongArch TCG keeps unchanged since I am not familiar with it. The maintainer duty will transfer to him after he comes back to work. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241112073714.1953481-1-maobibo@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-25plugins: detect qemu plugin API symbols from headerPierrick Bouvier1-0/+1
Instead of using a static file (error prone and hard to keep in sync), we generate it using a script. Note: if a symbol is not exported, we'll now notice it when linking for Windows/MacOS platforms. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241112212622.3590693-3-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241121165806.476008-37-alex.bennee@linaro.org>
2024-11-25tests/functional: Convert the Avocado aarch64 tuxrun testsThomas Huth1-1/+2
Move the tests to a new file so that they can be run via qemu-system-aarch64 in the functional framework. Since these were the last tests in tests/avocado/tuxrun_baselines.py, we can now remove that file, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241121165806.476008-20-alex.bennee@linaro.org>
2024-11-19Merge tag 'pull-9.2-rc-updates-181124-1' of https://gitlab.com/stsquad/qemu ↵Peter Maydell1-0/+5
into staging Misc fixes for 9.2 - fix remaining gdbstub test cases to exit cleanly - update MAINTAINERS with qemu-rust mailing list details - re-factor virtio-gpu and fix coverity warnings # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmc7aQwACgkQ+9DbCVqe # KkQufwf/XN5dcHxddhUHCLQUNA/5STiO5P10vHOGpknqwT/ZKADAbY8gQsoJovSp # qxczZPFpHlnGkf+AV3wrj2IcFUWlvlhgTw5njsMTOSSjK0jtI2MZrNn2v+6hmelg # y8ACB+LHkj34Ood9y5H6augCiKsMC7ad2mpXEMQgcZzpp4KlAutu8nbsYpYlAF40 # 1d2Wdtkrt++jPHQGgp0pPqAxq5WyvR3uSdidUFGfmpAqkCRs0ExosqEgj/ODzdHF # WrvLy9ISdCjZk+5XOxfadmz1vJ31QcZ6pcmkZRXJAJR4p7EST5BTfS10IBNIipgs # C25TuT+IH9+It0n/Sohf3NlxTnbTDw== # =TYAI # -----END PGP SIGNATURE----- # gpg: Signature made Mon 18 Nov 2024 16:19:24 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-9.2-rc-updates-181124-1' of https://gitlab.com/stsquad/qemu: hw/display: check frame buffer can hold blob hw/display: factor out the scanout blob to fb conversion MAINTAINERS: CC rust/ patches to qemu-rust list tests/tcg: Stop using exit() in the gdbstub testcases Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-18MAINTAINERS: CC rust/ patches to qemu-rust listManos Pitsidianakis1-0/+5
As of Nov 2024 [1], we have a new topical mailing list for Rust related patches. Add a new MAINTAINERS entry to touch all files under rust/ subdirectory and additionally add it to previous rust related entries. [1] https://lore.kernel.org/qemu-devel/CAFEAcA-ZQuyGTtG-vhRTEwpz0L4cpimNxkKix45Yw6gVHXozRQ@mail.gmail.com Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-Id: <20241109-update-maintainers-file-rust-v1-1-f4daba6f782f@linaro.org> [AJB: tweak commit msg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2024-11-18MAINTAINERS: Update my email address for COLOZhang Chen1-1/+1
Signed-off-by: Zhang Chen <chen.zhang@intel.com> Reviewed-by: Li Zhijian <lizhijian@fujitsu.com> Message-ID: <20241112084038.6352-1-chen.zhang@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-08tests/functional: Split the test_aarch64_sbsaref testThomas Huth1-1/+1
The test_aarch64_sbsaref test is the test with the longest runtime in our functional test suite. Split it into parts so that it can be run on multiple CPUs in parallel. For this we have to move the fetch_firmware() function out of the class definition to be able to reuse it easily from the other tests (deriving the Aarch64SbsarefAlpine and Aarch64SbsarefFreeBSD directly from Aarch64SbsarefMachine does not work, unfortunately, since we'd inherit the test_sbsaref_edk2_firmware() function that way, causing it to be run multiple times - and keeping the fetch_firmware() in a separate class without the test_sbsaref_edk2_firmware() function also does not work since the "make precache-functional" won't work in that case ==> turning fetch_firmware() into a static function is the best option). Message-ID: <20241106175029.1000589-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-08tests/functional: Convert the riscv_opensbi avocado test into a standalone testThomas Huth1-0/+1
The avocado test defined test functions for both, riscv32 and riscv64. Since we can run the whole file with multiple targets in the new framework, we can now consolidate the functions so we have to only define one function per machine now. Message-ID: <20240821082748.65853-23-thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-05Merge tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu ↵Peter Maydell1-4/+3
into staging * Various bug fixes * Big cleanup of deprecated machines * Power11 support for spapr * XIVE improvements * Goodbye to Cedric and David as ppc reviewers, thank you both o7 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmcoEicACgkQZ7MCdqhi # HK5M8Q//fz+ZkJndXkBjb1Oinx+q+eVtNm2JrvcWIsXyhG3K+6VxYPp69H+SRv/Z # TWuUqMQPxq8mhQvBJlDAttp/oaUEiOcCRvs/iUoBN12L4mVxXfdoT88TZ4frN3eP # 8bePq+DW2N/7gpmsJm5CyEZPpcf9AjVHgLRp3KYFkOJ/14uzvuwnocU39gl+2IUh # MXHTedQgMNXaKorJXk1NVdM6NxMuVhOvwxAs6ya2gwhxyA5tteo5PiQOnDJWkejf # xg3RRsNzGYcs1Qg/3kFIf3RfEB0aYbPxROM8IfPaJWKN5KnMggj/JAkHyK1x/V3J # wml7+cB0doMt/yRiuYJhXpyrtOqpvjRWPA6RhxECWW2kwrovv8NAF8IrFnw9NvOQ # QC66ZaaFcbAcFrVT1e/iggU76d01II6m4OAgKcXw+FRHgps4VU9y83j7ApNnNUWN # IXp9hkzoHi5VwX0FrG4ELUr2iEf1HASMvM8EZ/0AxzWj5iNtQB8lFsrEdaGVXyIS # M5JaJeNjCn4koCyYaFSctH5eKtbzIwnGWnDcdTwaOuQ+9itBvY8O+HZalE6sAc5S # kLFZ7i/Ut/qxbY5pMumt8LKD4pR1SsOxFB8dJCmn/f/tvRGtIVsoY6btNe4M0+24 # 42MxZbWO6W379C32bwbtsPiGA+aLSgShjP4cWm9cgRjz4RJFnwg= # =vmIG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Nov 2024 00:15:35 GMT # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE * tag 'pull-ppc-for-9.2-1-20241104' of https://gitlab.com/npiggin/qemu: (67 commits) MAINTAINERS: Remove myself as reviewer MAINTAINERS: Remove myself from XIVE MAINTAINERS: Remove myself from the PowerNV machines hw/ppc: Consolidate ppc440 initial mapping creation functions hw/ppc: Consolidate e500 initial mapping creation functions tests/qtest: Add XIVE tests for the powernv10 machine pnv/xive2: TIMA CI ops using alternative offsets or byte lengths pnv/xive2: TIMA support for 8-byte OS context push for PHYP pnv/xive: Update PIPR when updating CPPR pnv/xive: Add special handling for pool targets ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" ppc/xive2: Change context/ring specific functions to be generic ppc/xive2: Support "Pull Thread Context to Register" operation ppc/xive2: Allow 1-byte write of Target field in TIMA ppc/xive2: Dump the VP-group and crowd tables with 'info pic' ppc/xive2: Dump more NVP state with 'info pic' pnv/xive2: Support for "OS LGS Push" TIMA operation ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" pnv/xive2: Define OGEN field in the TIMA pnv/xive: TIMA patch sets pre-req alignment and formatting changes ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-04tests/functional: Convert the OrangePi tests to the functional frameworkThomas Huth1-0/+1
Move the OrangePi tests from tests/avocado/boot_linux_console.py into a new file dedicated for OrangePi tests in the functional framework and update the hash sums of the assets to sha256 along the way. For the buildroot image and the Armbian image, we've got to switch to a newer version since the old images have been removed from the server, and the NetBSD image has been moved to the archive, so we need to update this URL as well. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241029092440.25021-3-thuth@redhat.com>
2024-11-04tests/functional: Convert the tcg_plugins testThomas Huth1-1/+1
A straight forward conversion, only the usual changes were required here (i.e. adjustment for asset downloading, machine selection). Message-ID: <20241023051754.813412-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-04MAINTAINERS: Remove myself as reviewerDavid Gibson1-2/+0
I've now well and truly moved on from ppc and qemu maintenance. I'm occupied with other things and am pretty much just ignoring mails on these topics I'm CCed on. Time to remove myself. I'm still listed as a reviewer for Device Tree, I'll keep this for now, since I do have some interest and it's lower volume. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04MAINTAINERS: Remove myself from XIVECédric Le Goater1-1/+0
Working on XIVE has been one of the most complex and fascinating experiences for me. It's been a real journey, and now it's time for IBM to take over and guide its future. I'm stepping back as the maintainer of XIVE. Cc: Michael Kowal <kowal@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04MAINTAINERS: Remove myself from the PowerNV machinesCédric Le Goater1-1/+0
It's been an amazing experience working on PowerNV systems all these years. Now it's time for IBM to take the lead on the QEMU machine and shape its future. I'm stepping back as the maintainer of PowerNV. Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04tests/qtest: Add XIVE tests for the powernv10 machineFrederic Barrat1-0/+1
These XIVE tests include: - General interrupt IRQ tests that: - enable and trigger an interrupt - acknowledge the interrupt - end of interrupt processing - Test the Pull Thread Context to Odd Thread Reporting Line - Test the different cache flush inject and queue sync inject operations Co-authored-by: Frederic Barrat <fbarrat@linux.ibm.com> Co-authored-by: Glenn Miles <milesg@linux.ibm.com> Co-authored-by: Michael Kowal <kowal@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04MAINTAINERS: Cover PowerPC SPI model in PowerNV sectionPhilippe Mathieu-Daudé1-0/+2
It is unfair to let the PowerNV SPI model to the SSI maintainers. Also include the PowerNV ones. Fixes: 29318db133 ("hw/ssi: Add SPI model") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-02Merge tag 'for-upstream-i386' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-0/+21
* target/i386: new feature bits for AMD processors * target/i386/tcg: improvements around flag handling * target/i386: add AVX10 support * target/i386: add GraniteRapids-v2 model * dockerfiles: add libcbor * New nitro-enclave machine type * qom: cleanups to object_new * configure: detect 64-bit MIPS for rust * configure: deprecate 32-bit MIPS # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmcjvkQUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPIKgf/etNpO2T+eLFtWN/Qd5eopBXqNd9k # KmeK9EgW9lqx2IPGNen33O+uKpb/TsMmubSsSF+YxTp7pmkc8+71f3rBMaIAD02r # /paHSMVw0+f12DAFQz1jdvGihR7Mew0wcF/UdEt737y6vEmPxLTyYG3Gfa4NSZwT # /V5jTOIcfUN/UEjNgIp6NTuOEESKmlqt22pfMapgkwMlAJYeeJU2X9eGYE86wJbq # ZSXNgK3jL9wGT2XKa3e+OKzHfFpSkrB0JbQbdico9pefnBokN/hTeeUJ81wBAc7u # i00W1CEQVJ5lhBc121d4AWMp83ME6HijJUOTMmJbFIONPsITFPHK1CAkng== # =D4nR # -----END PGP SIGNATURE----- # gpg: Signature made Thu 31 Oct 2024 17:28:36 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream-i386' of https://gitlab.com/bonzini/qemu: (49 commits) target/i386: Introduce GraniteRapids-v2 model target/i386: Add AVX512 state when AVX10 is supported target/i386: Add feature dependencies for AVX10 target/i386: add CPUID.24 features for AVX10 target/i386: add AVX10 feature and AVX10 version property target/i386: return bool from x86_cpu_filter_features target/i386: do not rely on ExtSaveArea for accelerator-supported XCR0 bits target/i386: cpu: set correct supported XCR0 features for TCG target/i386: use + to put flags together target/i386: use higher-precision arithmetic to compute CF target/i386: use compiler builtin to compute PF target/i386: make flag variables unsigned target/i386: add a note about gen_jcc1 target/i386: add a few more trivial CCPrepare cases target/i386: optimize TEST+Jxx sequences target/i386: optimize computation of ZF from CC_OP_DYNAMIC target/i386: Wrap cc_op_live with a validity check target/i386: Introduce cc_op_size target/i386: Rearrange CCOp target/i386: remove CC_OP_CLR ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-31docs/nitro-enclave: Documentation for nitro-enclave machine typeDorjoy Chowdhury1-0/+1
Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Alexander Graf <graf@amazon.com> Link: https://lore.kernel.org/r/20241008211727.49088-7-dorjoychy111@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-31machine/nitro-enclave: New machine type for AWS Nitro EnclavesDorjoy Chowdhury1-0/+2
AWS nitro enclaves[1] is an Amazon EC2[2] feature that allows creating isolated execution environments, called enclaves, from Amazon EC2 instances which are used for processing highly sensitive data. Enclaves have no persistent storage and no external networking. The enclave VMs are based on the Firecracker microvm with a vhost-vsock device for communication with the parent EC2 instance that spawned it and a Nitro Secure Module (NSM) device for cryptographic attestation. The parent instance VM always has CID 3 while the enclave VM gets a dynamic CID. An EIF (Enclave Image Format)[3] file is used to boot an AWS nitro enclave virtual machine. This commit adds support for AWS nitro enclave emulation using a new machine type option '-M nitro-enclave'. This new machine type is based on the 'microvm' machine type, similar to how real nitro enclave VMs are based on Firecracker microvm. For nitro-enclave to boot from an EIF file, the kernel and ramdisk(s) are extracted into a temporary kernel and a temporary initrd file which are then hooked into the regular x86 boot mechanism along with the extracted cmdline. The EIF file path should be provided using the '-kernel' QEMU option. In QEMU, the vsock emulation for nitro enclave is added using vhost-user- vsock as opposed to vhost-vsock. vhost-vsock doesn't support sibling VM communication which is needed for nitro enclaves. So for the vsock communication to CID 3 to work, another process that does the vsock emulation in userspace must be run, for example, vhost-device-vsock[4] from rust-vmm, with necessary vsock communication support in another guest VM with CID 3. Using vhost-user-vsock also enables the possibility to implement some proxying support in the vhost-user-vsock daemon that will forward all the packets to the host machine instead of CID 3 so that users of nitro-enclave can run the necessary applications in their host machine instead of running another whole VM with CID 3. The following mandatory nitro-enclave machine option has been added related to the vhost-user-vsock device. - 'vsock': The chardev id from the '-chardev' option for the vhost-user-vsock device. AWS Nitro Enclaves have built-in Nitro Secure Module (NSM) device which has been added using the virtio-nsm device added in a previous commit. In Nitro Enclaves, all the PCRs start in a known zero state and the first 16 PCRs are locked from boot and reserved. The PCR0, PCR1, PCR2 and PCR8 contain the SHA384 hashes related to the EIF file used to boot the VM for validation. The following optional nitro-enclave machine options have been added related to the NSM device. - 'id': Enclave identifier, reflected in the module-id of the NSM device. If not provided, a default id will be set. - 'parent-role': Parent instance IAM role ARN, reflected in PCR3 of the NSM device. - 'parent-id': Parent instance identifier, reflected in PCR4 of the NSM device. [1] https://docs.aws.amazon.com/enclaves/latest/user/nitro-enclave.html [2] https://aws.amazon.com/ec2/ [3] https://github.com/aws/aws-nitro-enclaves-image-format [4] https://github.com/rust-vmm/vhost-device/tree/main/vhost-device-vsock Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Alexander Graf <graf@amazon.com> Link: https://lore.kernel.org/r/20241008211727.49088-6-dorjoychy111@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-31hw/core: Add Enclave Image Format (EIF) related helpersDorjoy Chowdhury1-0/+7
An EIF (Enclave Image Format)[1] file is used to boot an AWS nitro enclave[2] virtual machine. The EIF file contains the necessary kernel, cmdline, ramdisk(s) sections to boot. Some helper functions have been introduced for extracting the necessary sections from an EIF file and then writing them to temporary files as well as computing SHA384 hashes from the section data. These will be used in the following commit to add support for nitro-enclave machine type in QEMU. The files added in this commit are not compiled yet but will be added to the hw/core/meson.build file in the following commit where CONFIG_NITRO_ENCLAVE will be introduced. [1] https://github.com/aws/aws-nitro-enclaves-image-format [2] https://docs.aws.amazon.com/enclaves/latest/user/nitro-enclave.html Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Alexander Graf <graf@amazon.com> Link: https://lore.kernel.org/r/20241008211727.49088-4-dorjoychy111@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-31device/virtio-nsm: Support for Nitro Secure Module deviceDorjoy Chowdhury1-0/+10
Nitro Secure Module (NSM)[1] device is used in AWS Nitro Enclaves[2] for stripped down TPM functionality like cryptographic attestation. The requests to and responses from NSM device are CBOR[3] encoded. This commit adds support for NSM device in QEMU. Although related to AWS Nitro Enclaves, the virito-nsm device is independent and can be used in other machine types as well. The libcbor[4] library has been used for the CBOR encoding and decoding functionalities. [1] https://lists.oasis-open.org/archives/virtio-comment/202310/msg00387.html [2] https://docs.aws.amazon.com/enclaves/latest/user/nitro-enclave.html [3] http://cbor.io/ [4] https://libcbor.readthedocs.io/en/latest/ Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Alexander Graf <graf@amazon.com> Link: https://lore.kernel.org/r/20241008211727.49088-3-dorjoychy111@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-31MAINTAINERS: Add myself as a reviewer of x86 general architecture supportZhao Liu1-0/+1
X86 architecture has always been a focus of my work. I would like to help to review more related patches. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20241022023628.1743686-1-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-29docs/system/arm: Add placeholder docs for mcimx6ul-evk and mcimx7d-sabrePeter Maydell1-0/+2
Add placeholder docs for the mcimx6ul-evk and mcimx7d-sabre boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20241018141332.942844-7-peter.maydell@linaro.org
2024-10-29docs/system/arm: Add placeholder doc for xlnx-zcu102 boardPeter Maydell1-0/+1
Add a placeholder doc for the xlnx-zcu102 board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20241018141332.942844-6-peter.maydell@linaro.org
2024-10-29docs/system/arm: Add placeholder doc for exynos4 boardsPeter Maydell1-0/+1
Add a placeholder doc for the exynos4 boards nuri and smdkc210. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-id: 20241018141332.942844-5-peter.maydell@linaro.org
2024-10-29docs/system/arm: Split fby35 out from aspeed.rstPeter Maydell1-0/+1
The fby35 machine is not implemented in hw/arm/aspeed.c, but its documentation is currently stuck at the end of aspeed.rst, formatted in a way that it gets its own heading in the top-level list of boards in target-arm.html. We don't have any other boards that we document like this; split it out into its own rst file. This improves consistency with other board docs and means we can have the entry in the target-arm list be in the correct alphabetical order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Message-id: 20241018141332.942844-4-peter.maydell@linaro.org
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