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42 hoursbsd-user, linux-user: introduce qemu_process_cpu_eventsPaolo Bonzini25-23/+36
Add a user-mode emulation version of the function. More will be added later, for now it is just process_queued_cpu_work. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourstreewide: rename qemu_wait_io_event/qemu_wait_io_event_commonPaolo Bonzini11-15/+15
Do so before extending it to the user-mode emulators, where there is no such thing as an "I/O thread". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourscpus: properly kick CPUs out of inner execution loopPaolo Bonzini9-14/+17
Now that cpu_exit() actually kicks all accelerators, use it whenever the message to another thread is processed in qemu_wait_io_event(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourscpus: remove TCG-ism from cpu_exit()Paolo Bonzini1-3/+1
Now that TCG has its own kick function, make cpu_exit() do the right kick for all accelerators. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hoursaccel/tcg: inline cpu_exit()Paolo Bonzini1-2/+12
Right now, cpu_exit() is not usable from all accelerators because it includes a TCG-specific thread kick. In fact, cpu_exit() doubles as the TCG thread-kick via tcg_kick_vcpu_thread(). In preparation for changing that, inline cpu_exit() into tcg_kick_vcpu_thread(). The direction of the calls can then be reversed, with an accelerator-independent cpu_exit() calling into qemu_vcpu_kick() rather than the opposite. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hoursaccel/tcg: create a thread-kick function for TCGPaolo Bonzini10-21/+16
Round-robin TCG is calling into cpu_exit() directly. In preparation for making cpu_exit() usable from all accelerators, define a generic thread-kick function for TCG which is used directly in the multi-threaded case, and through CPU_FOREACH in the round-robin case. Use it also for user-mode emulation, and take the occasion to move the implementation to accel/tcg/user-exec.c. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hoursaccel: use atomic accesses for exit_requestPaolo Bonzini9-15/+24
CPU threads write exit_request as a "note to self" that they need to go out to a slow path. This write happens out of the BQL and can be a data race with another threads' cpu_exit(); use atomic accesses consistently. While at it, change the source argument from int ("1") to bool ("true"). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hoursaccel: use store_release/load_acquire for cross-thread exit_requestPaolo Bonzini6-19/+29
Reads and writes cpu->exit_request do not use a load-acquire/store-release pair right now, but this means that cpu_exit() may not write cpu->exit_request after any flags that are read by the vCPU thread. Probably everything is protected one way or the other by the BQL, because cpu->exit_request leads to the slow path, where the CPU thread often takes the BQL (for example, to go to sleep by waiting on the BQL-protected cpu->halt_cond); but it's not clear, so use load-acquire/store-release consistently. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourscpus: document that qemu_cpu_kick() can be used for BQL-less operationPaolo Bonzini1-1/+2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourscpu-common: use atomic access for interrupt_requestPaolo Bonzini3-14/+2
Writes to interrupt_request used non-atomic accesses, but there are a few cases where the access was not protected by the BQL. Now that there is a full set of helpers, it's easier to guarantee that interrupt_request accesses are fully atomic, so just drop the requirement instead of fixing them. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourstreewide: clear bits of cs->interrupt_request with cpu_reset_interrupt()Paolo Bonzini12-40/+39
Open coding cpu_reset_interrupt() can cause bugs if the BQL is not taken, for example i386 has the call chain kvm_cpu_exec() -> kvm_put_vcpu_events() -> kvm_arch_put_registers(). Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hoursuser-exec: remove cpu_interrupt() stubPaolo Bonzini1-5/+0
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourstarget-arm: remove uses of cpu_interrupt() for user-mode emulationPaolo Bonzini6-370/+429
Arm leaves around some functions that use cpu_interrupt(), even for user-mode emulation when the code is unreachable. Pull out the system-mode implementation to a separate file, and add stubs for CONFIG_USER_ONLY. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourstarget/i386: limit a20 to system emulationPaolo Bonzini1-0/+2
It is not used by user-mode emulation and is the only caller of cpu_interrupt() in qemu-i386 and qemu-x86_64. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourstarget/sparc: limit cpu_check_irqs to system emulationPaolo Bonzini2-0/+4
It is not used by user-mode emulation and is the only caller of cpu_interrupt() in qemu-sparc* binaries. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hourstarget/ppc: limit cpu_interrupt_exittb to system emulationPaolo Bonzini1-0/+2
It is not used by user-mode emulation and is the only caller of cpu_interrupt() in qemu-ppc* binaries. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
42 hoursMerge tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu into ↵Richard Henderson36-21/+826
staging Pull request Daniel's updated tracetool test suite that doesn't break Windows CI. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmjJo2gACgkQnKSrs4Gr # c8gAWggAmFCi3KyeoJYLdw8ANZ46lDPV+GCtTKtCM68LtcSZKfrlNROWE/9UDI7V # P3U/Xog01mqyWw4RX+SC90ckSWchMcLSN+TT8mZNfOTn8mcelyQkh4TDlguBLxlE # Qz8PMwIxrKljP0bV9evZ1gk1CHkB8u1jPKLckiZRdI9rbjuxNkYTMyVSezCdfIhV # dTDO1xf3oTDZq94591D0jSLHuF58MNXJHlA/q5OIdPCqu80Vo6cc8A8B5E1ZGKA5 # wzXaMY72GlX8RYwebXudHI0Sen6XyE3It+iWQYD8o6kgJ6kxBc0ljLxJCRE9O/d4 # D5hBgEgJ5S1ul4ggkBf5UKazF86EIQ== # =YODs # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 Sep 2025 10:50:32 AM PDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [unknown] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu: tracetool-test: allow to run in parallel qapi: switch to use QEMU_TEST_REGENERATE env var tracetool: drop the probe "__nocheck__" wrapping tracetool: add test suite for tracetool with reference output tracetool: include SPDX-License-Identifier in generated files tracetool: avoid space after "*" in arg types tracetool: eliminate trailing whitespace in C format checkpatch: cull trailing '*/' in SPDX check Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 daystracetool-test: allow to run in parallelMarc-André Lureau1-3/+5
Create a temporary build subdirectory, to avoid conflicting with other running tests. This fixes "meson test" with tracetool-test which is parallel default. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20250916081638.764020-9-berrange@redhat.com Message-ID: <20250908114652.1880366-1-marcandre.lureau@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daysqapi: switch to use QEMU_TEST_REGENERATE env varDaniel P. Berrangé2-2/+17
The QAPI_TEST_UPDATE env var can be set when running the QAPI schema tests to regenerate the reference output. For consistent naming with the tracetool test, change the env var name to QEMU_TEST_REGENERATE. The test is modified to provide a hint about use of the new env var and it is also added to the developer documentation.document its usage. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 20250916081638.764020-8-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daystracetool: drop the probe "__nocheck__" wrappingDaniel P. Berrangé8-115/+16
Every generated inline probe function is wrapped with a trivial caller that has a hard-coded condition test: static inline void _nocheck__trace_test_wibble(void * context, int value) { tracepoint(qemu, test_wibble, context, value); } static inline void trace_test_wibble(void * context, int value) { if (true) { _nocheck__trace_test_wibble(context, value); } } This was introduced for TCG probes back in 864a2178: trace: [tcg] Do not generate TCG code to trace dynamically-disabled events but is obsolete since 126d4123 tracing: excise the tcg related from tracetool This commit removes the wrapping such that we have static inline void trace_test_wibble(void * context, int value) { tracepoint(qemu, test_wibble, context, value); } The default build of qemu-system-x86_64 on Fedora with the 'log' backend, has its size reduced by 1 MB Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20250916081638.764020-7-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daystracetool: add test suite for tracetool with reference outputDaniel P. Berrangé25-0/+870
When reviewing tracetool patches it is often very unclear what the expected output will be for the generated backends. Compounding this is that a default build will only enable the 'log' trace backend, so developers won't see generated code for other backends without making a special effort. Some backends are also platform specific, so can't be enabled in QEMU builds, even though tracetool could generate the code. To address this, introduce a test suite for tracetool which is conceptually similar to the qapi-schema test. It is a simple python program that runs tracetool and compares the actual output to historical reference output kept in git. The test directly emits TAP format logs for ease of integration with meson. This can be run with make check-tracetool to make it easier for developers changing generated output, the sample expected content can be auto-recreated QEMU_TEST_REGENERATE=1 make check-tracetool and the changes reviewed and added to the commit. This will also assist reviewers interpreting the change. Developers are reminded of this in the test output on failure: $ make check-tracetool 1/6 qemu:tracetool / dtrace OK 0.14s 2/6 qemu:tracetool / ftrace FAIL 0.06s exit status 1 ―――――――――――――――――――――――――――――――――――――――――――――――――――――――――― 1..2 ok 1 - ftrace.c # not ok 1 - ftrace.h (set QEMU_TEST_REGENERATE=1 to recreate reference output if tracetool generator was intentionally changed) ―――――――――――――――――――――――――――――――――――――――――――――――――――――――――― 3/6 qemu:tracetool / log OK 0.06s 4/6 qemu:tracetool / simple OK 0.06s 5/6 qemu:tracetool / syslog OK 0.06s 6/6 qemu:tracetool / ust OK 0.11s Summary of Failures: 2/6 qemu:tracetool / ftrace FAIL 0.06s exit status 1 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20250916081638.764020-6-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daystracetool: include SPDX-License-Identifier in generated filesDaniel P. Berrangé8-1/+9
While these files are auto-generated, a later commit will add reference output to git, so having SPDX-License-Identifier is desirable. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20250916081638.764020-5-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daystracetool: avoid space after "*" in arg typesDaniel P. Berrangé1-1/+7
QEMU code style is to have no whitespace between "*" and the arg name. Since generated trace code will soon be added to git, make it comply with code style. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20250916081638.764020-4-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daystracetool: eliminate trailing whitespace in C formatDaniel P. Berrangé1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20250916081638.764020-3-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 dayscheckpatch: cull trailing '*/' in SPDX checkDaniel P. Berrangé1-0/+3
Sometimes SPDX expressions appear inside C comments, and this confuses checkpatch.pl. Drop the closing C comment characters to avoid this. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20250916081638.764020-2-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
3 daysMerge tag 'pull-misc-20250916' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson2-3/+4
.gitmodules: move u-boot mirrors to qemu-project-mirrors tests/functional/x86_64: Accept a few locked pages in test_memlock.py # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmjJmVwdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+RMQf/e2ScmOiJaD/5ba5i # RPZneCUOV0AkVSpAwxKX9M1Gsroz/NZefVp9yh2wPdcoAPnLjoFJaJuEv1jEPPVh # /RApI2NehuqWTzndY0dci6vV6YzxLoMZsQWoBRz0l3SfzVq0YuePSlV+YkTMSfgX # z9ocwPwGG0AEYvEllVPq5UVHZlEoE4BE23QyHtyuXRwjqo3BHjJKQXBK4hA5vAYQ # gbWiFs3QJ+fsKQk7Z2KJDc6k4H/Oql4T2bILGjQRb9DG4yR1TIvwIsbOj2dFHVrs # 6HdP5e6PweuHGc8mdFEHJFgZrdA8exxwT0lq/5vYxvjf86nick+z3XrhOXWoHq6G # L6OgLg== # =YBDc # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 Sep 2025 10:07:40 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-misc-20250916' of https://gitlab.com/rth7680/qemu: .gitmodules: move u-boot mirrors to qemu-project-mirrors tests/functional/x86_64: Accept a few locked pages in test_memlock.py Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 daysMerge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into stagingRichard Henderson18-326/+529
Python Pull Request Python 3.14 support & synchronize with python-qemu-qmp repo # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEE+ber27ys35W+dsvQfe+BBqr8OQ4FAmjJjxIACgkQfe+BBqr8 # OQ48aA/+JRRIEN8LMbNDRvPTTkvCxstSAb2q8yA+8ccWg0H+EGcewjd+oCoPOqjC # SwIMAGYJ6Dv2LW6c+rK6VjKw1Da8J9WgEpKmfoWu+1Pef8odU5PoRhAvvZdMq+Eh # Kqk0r1f87fTiZK1gCBhBUIO0oTroOYxDvIYV0B6UFDPArL8jJ5eTpGLCVAYuk8tH # MuzQD0IcxCBoraOx9vqVMbKIHwMH/m9pJ2IqINzIStpLoFgT1d5V9CoKXImMVXmF # XovcMWQzFz1a/lm0ybSAzhgXcpW/vNjstb1IcrigYjQWXU6S+/bRpq17c2WqAJtG # 78Dal7heSjpvWyyCCii+QO+BegH53Mgz3W+aQN7+fkcepjivVYy8tnxOrSjJR+pX # DqRhMNSc4CrLvJH4BOHKUsJaWMxjd4oJiNhUmhJ7MxZhPTHZvERsOo9kpoJo4eTw # GhRV98FnJbotgs2kjQpSBF8FDj9LZqPwTfMuEU2NUsIB9o7/Iqj36RDe9L+2r9Ch # 2UKhnUg58y4eYFoC4CO8yCfjsR6HzLdqiVaDhcu5pdQM0Dw1pxrSIHb6faNmSLL5 # v0brhgJGujWt6wAc2c3ASMf8qpWkBrlVfHybodOB2cUDcRgNk85M/s41PnGShqBZ # Qq7VW9zR4sejwof9dTwYKuwsNzxzFdS2nLwPPkud5aDngrLsNn0= # =jZpa # -----END PGP SIGNATURE----- # gpg: Signature made Tue 16 Sep 2025 09:23:46 AM PDT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * tag 'python-pull-request' of https://gitlab.com/jsnow/qemu: iotests/check: always enable all python warnings iotests/151: ensure subprocesses are cleaned up iotests/147: ensure temporary sockets are closed before exiting python: ensure QEMUQtestProtocol closes its socket iotests: drop compat for old version context manager python: synchronize qemu.qmp documentation python: backport 'avoid creating additional event loops per thread' python: backport 'Remove deprecated get_event_loop calls' python: backport 'qmp-tui: Do not crash if optional dependencies are not met' python: backport 'qmp-shell-wrap: handle missing binary gracefully' python: backport 'make require() preserve async-ness' python: backport 'feat: allow setting read buffer limit' python: backport 'qmp-shell: add common_parser()' python: backport 'Use @asynciocontextmanager' python: backport 'drop Python3.6 workarounds' python: backport 'protocol: adjust logging name when changing client name' python: backport 'kick event queue on legacy event_pull()' python: backport 'EventListener: add __repr__ method' python: backport 'Change error classes to have better repr methods' Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 daysMerge tag 'mem-staging-pull-request' of https://gitlab.com/peterx/qemu into ↵Richard Henderson3-13/+44
staging Memory pull for 10.2 - Peter's fix on flatview_access_allowed() - Peter's fix on MR circular ref # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCaMg4oxIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wYeLAD+LQ44LdRTjbdlAbDjSNnCorfEBFUmNysK # St4ut4Z9ZzAA+gK8DO12zc41Oi51NaBdD+X0s94DCV4UFl4Cz1D8HoIF # =hAUJ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 15 Sep 2025 09:02:43 AM PDT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [unknown] # gpg: aka "Peter Xu <peterx@redhat.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'mem-staging-pull-request' of https://gitlab.com/peterx/qemu: memory: Fix leaks due to owner-shared MRs circular references memory: Fix addr/len for flatview_access_allowed() Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 days.gitmodules: move u-boot mirrors to qemu-project-mirrorsAlex Bennée1-2/+2
To continue our GitLab Open Source Program license we need to pass an automated license check for all repos under qemu-project. While U-Boot is clearly GPLv2 rather than fight with the automated validation script just move the mirror across to a separate project. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250908141911.2546063-1-alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 daystests/functional/x86_64: Accept a few locked pages in test_memlock.pyRichard Henderson1-1/+2
Startup of libgcrypt locks a small pool of pages -- by default 16k. Testing for zero locked pages is isn't correct, while testing for 32k is a decent compromise. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 dayshw/usb/network: Remove hardcoded 0x40 prefix in STRING_ETHADDR responseStéphane Graber1-1/+1
USB NICs have a "40:" prefix hardcoded for all MAC addresses when we return the guest the MAC address if it queries the STRING_ETHADDR USB string property. This doesn't match what we use for the OID_802_3_PERMANENT_ADDRESS or OID_802_3_CURRENT_ADDRESS OIDs for NDIS, or the MAC address we actually use in the QEMU networking code to send/receive packets for this device, or the NIC info string we print for users. In all those other places we directly use s->conf.macaddr.a, which is the full thing the user asks for. This overrides user-provided configuration and leads to an inconsistent experience. I couldn't find any documented reason (comment or git commits) for this behavior. It seems like everyone is just expecting the MAC address to be fully passed through to the guest, but it isn't. This may have been a debugging hack that accidentally made it through to the accepted patch: it has been in the code since it was originally added back in 2008. This is also particularly problematic as the "40:" prefix isn't a reserved prefix for MAC addresses (IEEE OUI). There are a number of valid allocations out there which use this prefix, meaning that QEMU may be causing MAC address conflicts. Cc: qemu-stable@nongnu.org Fixes: 6c9f886ceae5b ("Add CDC-Ethernet usb NIC (original patch from Thomas Sailer)" Signed-off-by: Stéphane Graber <stgraber@stgraber.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2951 Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> [PMM: beef up commit message based on mailing list discussion] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daysqtest/bios-tables-test: Update tables for smmuv3 testsShameer Kolothum5-4/+0
For the legacy smmuv3 test case, generated IORT has a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node. RC node features 4 ID mappings, of which 2 points to SMMU node and the remaining ones points to ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU0} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} ... [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 01 [034h 0052 4] Identifier : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 04 [049h 0073 2] Length : 0058 [04Bh 0075 1] Revision : 04 [04Ch 0076 4] Identifier : 00000001 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000044 [058h 0088 8] Base Address : 0000000009050000 [060h 0096 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [064h 0100 4] Reserved : 00000000 [068h 0104 8] VATOS Address : 0000000000000000 [070h 0112 4] Model : 00000000 [074h 0116 4] Event GSIV : 0000006A [078h 0120 4] PRI GSIV : 0000006B [07Ch 0124 4] GERR GSIV : 0000006D [080h 0128 4] Sync GSIV : 0000006C [084h 0132 4] Proximity Domain : 00000000 [088h 0136 4] Device ID Mapping Index : 00000000 [08Ch 0140 4] Input base : 00000000 [090h 0144 4] ID Count : 0000FFFF [094h 0148 4] Output Base : 00000000 [098h 0152 4] Output Reference : 00000030 [09Ch 0156 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 1] Type : 02 [0A1h 0161 2] Length : 0074 [0A3h 0163 1] Revision : 03 [0A4h 0164 4] Identifier : 00000002 [0A8h 0168 4] Mapping Count : 00000004 [0ACh 0172 4] Mapping Offset : 00000024 [0B0h 0176 8] Memory Properties : [IORT Memory Access Properties] [0B0h 0176 4] Cache Coherency : 00000001 [0B4h 0180 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [0B5h 0181 2] Reserved : 0000 [0B7h 0183 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [0B8h 0184 4] ATS Attribute : 00000000 [0BCh 0188 4] PCI Segment Number : 00000000 [0C0h 0192 1] Memory Size Limit : 40 [0C1h 0193 2] PASID Capabilities : 0000 [0C3h 0195 1] Reserved : 00 [0C4h 0196 4] Input base : 00000000 [0C8h 0200 4] ID Count : 000001FF [0CCh 0204 4] Output Base : 00000000 [0D0h 0208 4] Output Reference : 00000048 [0D4h 0212 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0D8h 0216 4] Input base : 00001000 [0DCh 0220 4] ID Count : 000000FF [0E0h 0224 4] Output Base : 00001000 [0E4h 0228 4] Output Reference : 00000048 [0E8h 0232 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0ECh 0236 4] Input base : 00000200 [0F0h 0240 4] ID Count : 00000DFF [0F4h 0244 4] Output Base : 00000200 [0F8h 0248 4] Output Reference : 00000030 [0FCh 0252 4] Flags (decoded below) : 00000000 Single Mapping : 0 [100h 0256 4] Input base : 00001100 [104h 0260 4] ID Count : 0000EEFF [108h 0264 4] Output Base : 00001100 [10Ch 0268 4] Output Reference : 00000030 [110h 0272 4] Flags (decoded below) : 00000000 Single Mapping : 0 For the smmuv3-dev test case, IORT has 2 SMMUV3 nodes, 1 RC node and 1 ITS node. RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while the others targets the ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU1} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} ... [030h 0048 1] Type : 00 [031h 0049 2] Length : 0018 [033h 0051 1] Revision : 01 [034h 0052 4] Identifier : 00000000 [038h 0056 4] Mapping Count : 00000000 [03Ch 0060 4] Mapping Offset : 00000000 [040h 0064 4] ItsCount : 00000001 [044h 0068 4] Identifiers : 00000000 [048h 0072 1] Type : 04 [049h 0073 2] Length : 0058 [04Bh 0075 1] Revision : 04 [04Ch 0076 4] Identifier : 00000001 [050h 0080 4] Mapping Count : 00000001 [054h 0084 4] Mapping Offset : 00000044 [058h 0088 8] Base Address : 000000000C000000 [060h 0096 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [064h 0100 4] Reserved : 00000000 [068h 0104 8] VATOS Address : 0000000000000000 [070h 0112 4] Model : 00000000 [074h 0116 4] Event GSIV : 00000090 [078h 0120 4] PRI GSIV : 00000091 [07Ch 0124 4] GERR GSIV : 00000093 [080h 0128 4] Sync GSIV : 00000092 [084h 0132 4] Proximity Domain : 00000000 [088h 0136 4] Device ID Mapping Index : 00000000 [08Ch 0140 4] Input base : 00000000 [090h 0144 4] ID Count : 0000FFFF [094h 0148 4] Output Base : 00000000 [098h 0152 4] Output Reference : 00000030 [09Ch 0156 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0A0h 0160 1] Type : 04 [0A1h 0161 2] Length : 0058 [0A3h 0163 1] Revision : 04 [0A4h 0164 4] Identifier : 00000002 [0A8h 0168 4] Mapping Count : 00000001 [0ACh 0172 4] Mapping Offset : 00000044 [0B0h 0176 8] Base Address : 000000000C020000 [0B8h 0184 4] Flags (decoded below) : 00000001 COHACC Override : 1 HTTU Override : 0 Proximity Domain Valid : 0 [0BCh 0188 4] Reserved : 00000000 [0C0h 0192 8] VATOS Address : 0000000000000000 [0C8h 0200 4] Model : 00000000 [0CCh 0204 4] Event GSIV : 00000094 [0D0h 0208 4] PRI GSIV : 00000095 [0D4h 0212 4] GERR GSIV : 00000097 [0D8h 0216 4] Sync GSIV : 00000096 [0DCh 0220 4] Proximity Domain : 00000000 [0E0h 0224 4] Device ID Mapping Index : 00000000 [0E4h 0228 4] Input base : 00000000 [0E8h 0232 4] ID Count : 0000FFFF [0ECh 0236 4] Output Base : 00000000 [0F0h 0240 4] Output Reference : 00000030 [0F4h 0244 4] Flags (decoded below) : 00000000 Single Mapping : 0 [0F8h 0248 1] Type : 02 [0F9h 0249 2] Length : 0074 [0FBh 0251 1] Revision : 03 [0FCh 0252 4] Identifier : 00000003 [100h 0256 4] Mapping Count : 00000004 [104h 0260 4] Mapping Offset : 00000024 [108h 0264 8] Memory Properties : [IORT Memory Access Properties] [108h 0264 4] Cache Coherency : 00000001 [10Ch 0268 1] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [10Dh 0269 2] Reserved : 0000 [10Fh 0271 1] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [110h 0272 4] ATS Attribute : 00000000 [114h 0276 4] PCI Segment Number : 00000000 [118h 0280 1] Memory Size Limit : 40 [119h 0281 2] PASID Capabilities : 0000 [11Bh 0283 1] Reserved : 00 [11Ch 0284 4] Input base : 00000000 [120h 0288 4] ID Count : 000001FF [124h 0292 4] Output Base : 00000000 [128h 0296 4] Output Reference : 00000048 [12Ch 0300 4] Flags (decoded below) : 00000000 Single Mapping : 0 [130h 0304 4] Input base : 00001000 [134h 0308 4] ID Count : 000000FF [138h 0312 4] Output Base : 00001000 [13Ch 0316 4] Output Reference : 000000A0 [140h 0320 4] Flags (decoded below) : 00000000 Single Mapping : 0 [144h 0324 4] Input base : 00000200 [148h 0328 4] ID Count : 00000DFF [14Ch 0332 4] Output Base : 00000200 [150h 0336 4] Output Reference : 00000030 [154h 0340 4] Flags (decoded below) : 00000000 Single Mapping : 0 [158h 0344 4] Input base : 00001100 [15Ch 0348 4] ID Count : 0000EEFF [160h 0352 4] Output Base : 00001100 [164h 0356 4] Output Reference : 00000030 [168h 0360 4] Flags (decoded below) : 00000000 Single Mapping : 0 Note: DSDT changes are not described here as it is not impacted by the way the SMMUv3 is instantiated. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-12-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daysqtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 deviceShameer Kolothum1-0/+86
For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes, one of which has bypass_iommu enabled. The generated IORT table contains a single SMMUv3 node, a Root Complex(RC) node and 1 ITS node. RC node features 4 ID mappings, of which 2 points to SMMU node and the remaining ones points to ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU0} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} For the -device arm-smmuv3,... test, the configuration also includes three Root Complexes, with two connected to separate SMMUv3 devices. The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node. RC node features 4 ID mappings. 2 of them target the 2 SMMU nodes while the others targets the ITS. pcie.0 -> {SMMU0} -> {ITS} {RC} pcie.1 -> {SMMU1} -> {ITS} pcie.2 -> {ITS} [all other ids] -> {ITS} Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-11-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daysbios-tables-test: Allow for smmuv3 test data.Shameer Kolothum5-0/+4
The tests to be added exercise both legacy(iommu=smmuv3) and new -device arm-smmuv3,.. cases. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-10-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daysqemu-options.hx: Document the arm-smmuv3 deviceShameer Kolothum1-0/+7
Now that arm,virt can have user-creatable smmuv3 devices, document it. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-9-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/arm/virt: Allow user-creatable SMMUv3 dev instantiationShameer Kolothum5-1/+64
Allow cold-plugging of an SMMUv3 device on the virt machine when no global (legacy) SMMUv3 is present or when a virtio-iommu is specified. This user-created SMMUv3 device is tied to a specific PCI bus provided by the user, so ensure the IOMMU ops are configured accordingly. Due to current limitations in QEMU’s device tree support, specifically its inability to properly present pxb-pcie based root complexes and their devices, the device tree support for the new SMMUv3 device is limited to cases where it is attached to the default pcie.0 root complex. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-8-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrievalShameer Kolothum3-0/+34
Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus. However, when retrieving IOMMU ops for a device using pci_device_get_iommu_bus_devfn(), the function checks the parent_dev and fetches IOMMU ops from the parent device, even if the current bus does not have any associated IOMMU ops. This behavior works for now because QEMU's IOMMU implementations are globally scoped, and host bridges rely on the bypass_iommu property to skip IOMMU translation when needed. However, this model will break with the soon to be introduced arm-smmuv3 device, which allows users to associate the IOMMU with a specific PCIe root complex (e.g., the default pcie.0 or a pxb-pcie root complex). For example, consider the following setup with multiple root complexes: -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0 \ ... -device pxb-pcie,id=pcie.1,bus_nr=8,bus=pcie.0 \ -device pcie-root-port,id=pcie.port1,bus=pcie.1 \ -device virtio-net-pci,bus=pcie.port1 In Qemu, pxb-pcie acts as a special root complex whose parent is effectively the default root complex(pcie.0). Hence, though pcie.1 has no associated SMMUv3 as per above, pci_device_get_iommu_bus_devfn() will incorrectly return the IOMMU ops from pcie.0 due to the fallback via parent_dev. To fix this, introduce a new helper pci_setup_iommu_per_bus() that explicitly sets the new iommu_per_bus field in the PCIBus structure. This helper will be used in a subsequent patch that adds support for the new arm-smmuv3 device. Update pci_device_get_iommu_bus_devfn() to use iommu_per_bus when determining the correct IOMMU ops, ensuring accurate behavior for per-bus IOMMUs. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-7-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/arm/virt: Add an SMMU_IO_LEN macroNicolin Chen1-1/+4
This is useful as the subsequent support for new SMMUv3 dev will also use the same. Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250829082543.7680-6-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/arm/virt: Factor out common SMMUV3 dt bindings codeShameer Kolothum1-25/+29
No functional changes intended. This will be useful when we add support for user-creatable smmuv3 device. Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-5-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devicesShameer Kolothum1-0/+64
With the soon to be introduced user-creatable SMMUv3 devices for virt, it is possible to have multiple SMMUv3 devices associated with different PCIe root complexes. Update IORT nodes accordingly. An example IORT Id mappings for a Qemu virt machine with two PCIe Root Complexes each assocaited with a SMMUv3 will be something like below, -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0 -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1 ... +--------------------+ +--------------------+ | Root Complex 0 | | Root Complex 1 | | | | | | Requestor IDs | | Requestor IDs | | 0x0000 - 0x00FF | | 0x0100 - 0x01FF | +---------+----------+ +---------+----------+ | | | | | Stream ID Mapping | v v +--------------------+ +--------------------+ | SMMUv3 Node 0 | | SMMUv3 Node 1 | | | | | | Stream IDs 0x0000- | | Stream IDs 0x0100- | | 0x00FF mapped from | | 0x01FF mapped from | | RC0 Requestor IDs | | RC1 Requestor IDs | +--------------------+ +--------------------+ | | | | +----------------+---------------+ | |Device ID Mapping v +----------------------------+ | ITS Node 0 | | | | Device IDs: | | 0x0000 - 0x00FF (from RC0) | | 0x0100 - 0x01FF (from RC1) | | 0x0200 - 0xFFFF (No SMMU) | +----------------------------+ Tested-by: Nathan Chen <nathanc@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-4-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT buildShameer Kolothum3-45/+94
Introduce a new struct AcpiIortSMMUv3Dev to hold all the information required for SMMUv3 IORT node and use that for populating the node. The current machine wide SMMUv3 is named as legacy SMMUv3 as we will soon add support for user-creatable SMMUv3 devices. These changes will be useful to have common code paths when we add that support. Tested-by: Nathan Chen <nathanc@nvidia.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-3-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayshw/arm/smmu-common: Check SMMU has PCIe Root Complex associationShameer Kolothum3-4/+29
We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based extra root complexes to be associated with SMMU. Although this change does not affect functionality at present, it is required when we add support for user-creatable SMMUv3 devices in future patches. Note: Added a specific check to identify pxb-pcie to avoid matching pxb-cxl host bridges, which are also of type PCI_HOST_BRIDGE. This restriction can be relaxed once support for CXL devices on arm/virt is added and validated with SMMUv3. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Nathan Chen <nathanc@nvidia.com> Tested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com> Reviewed-by: Donald Dutile <ddutile@redhat.com> Message-id: 20250829082543.7680-2-skolothumtho@nvidia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daystarget/arm: Added test case for SME register exposure to GDBVacha Bhavsar3-0/+152
This patch adds a test case to test SME register exposure to a remote gdb debugging session. This test simply sets and reads SME registers. Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> Message-id: 20250909161012.2561593-4-vacha.bhavsar@oss.qualcomm.com [PMM: fixed various python formatting nits] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daystarget/arm: Added support for SME register exposure to GDBVacha Bhavsar4-1/+132
The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality for AArch64 targets, this patch registers the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Note that according to the GDB documentation the ZA register is defined as a vector of bytes; however the target description xml retrieved when using gdb natively on a host with SME capabilities represents the ZA register as a vector of vectors of bytes, so this is a GDB documentation error. We follow GDB's own gdbstub implementation and represent the ZA register as a vector of vectors of bytes as is done by GDB here: https://github.com/bminor/binutils-gdb/blob/5cce2b7006daa7073b98e3d1a3b176199d1381d7/gdb/features/aarch64-sme.c#L50 Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> Message-id: 20250909161012.2561593-3-vacha.bhavsar@oss.qualcomm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed minor checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daystarget/arm: Increase MAX_PACKET_LENGTH for SME ZA remote gdb debuggingVacha Bhavsar1-1/+21
This patch increases the value of the MAX_PACKET_LEGNTH to 131104 from 4096 to allow the GDBState.line_buf to be large enough to accommodate the full contents of the SME ZA storage when the vector length is maximal. This is in preparation for a related patch that allows SME register visibility through remote GDB debugging. Signed-off-by: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250909161012.2561593-2-vacha.bhavsar@oss.qualcomm.com [PMM: fixed up comment formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 daysarm/kvm: report registers we failed to setCornelia Huck1-0/+86
If we fail migration because of a mismatch of some registers between source and destination, the error message is not very informative: qemu-system-aarch64: error while loading state for instance 0x0 ofdevice 'cpu' qemu-system-aarch64: Failed to put registers after init: Invalid argument At least try to give the user a hint which registers had a problem, even if they cannot really do anything about it right now. Sample output: Could not set register op0:3 op1:0 crn:0 crm:0 op2:0 to c00fac31 (is 413fd0c1) We could be even more helpful once we support writable ID registers, at which point the user might actually be able to configure something that is migratable. Suggested-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Sebastian Ott <sebott@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20250911154159.158046-1-cohuck@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3 dayssystem: drop the -old-param optionPeter Maydell7-106/+13
We deprecated the command line option -old-param for the 10.0 release, which allows us to drop it in 10.2. This option was used to boot Arm targets with a very old boot protocol using the 'param_struct' ABI. We only ever needed this on a handful of board types which have all now been removed from QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250828162700.3308812-1-peter.maydell@linaro.org
3 daystarget/arm: Drop ARM_FEATURE_IWMMXT handlingPeter Maydell6-117/+0
We have now removed all the CPU types which had the Intel XScale extensions indicated via ARM_FEATURE_IWMMXT, so this feature bit is never set. Remove all the code that can only be reached when using this flag. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250828140422.3271703-6-peter.maydell@linaro.org
3 daystarget/arm: Drop ARM_FEATURE_XSCALE handlingPeter Maydell5-80/+3
We have now removed all the CPU types which had the Intel XScale extensions indicated via ARM_FEATURE_XSCALE, so this feature bit is never set. Remove all the code that can only be reached when using this flag. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250828140422.3271703-5-peter.maydell@linaro.org
3 daystarget/arm: Remove iwmmxt helper functionsPeter Maydell3-769/+0
Remove the iwmmxt helper functions which are no longer called now that we have removed the associated translate.c handling. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250828140422.3271703-4-peter.maydell@linaro.org
generated by cgit v1.1 at 2025-09-19 10:56:21 +0000