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2025-03-21ppc/spapr: fix default cpu for pre-9.0 machines.Harsh Prateek Bora1-0/+1
When POWER10 CPU was made as default, we missed keeping POWER9 as default for older pseries releases (pre-9.0) at that time. This caused breakge in default cpu evaluation for older pseries machines and hence this fix. Fixes: 51113013f3 ("ppc/spapr: change pseries machine default to POWER10 CPU") Cc: qemu-stable@nongnu.org Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250313094705.2361997-1-harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-21ppc/amigaone: Constify default_envBALATON Zoltan1-1/+1
The variable holding default env is not supposed to be written. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250314200145.08E0F4E6067@zero.eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-21ppc/amigaone: Check blk_pwrite return valueBALATON Zoltan1-6/+8
Coverity reported that return value of blk_pwrite() maybe should not be ignored. We can't do much if this happens other than report an error but let's do that to silence this report. Resolves: Coverity CID 1593725 Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20250314200140.2DBE74E6069@zero.eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-21target/loongarch: fix bad shift in check_ps()Song Gao3-7/+7
In expression 1ULL << tlb_ps, left shifting by more than 63 bits has undefined behavior. The shift amount, tlb_ps, is as much as 64. check "tlb_ps >=64" to fix. Resolves: Coverity CID 1593475 Fixes: d882c284a3 ("target/loongarch: check tlb_ps") Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-21docs/system: Add entry for LoongArch systemBibo Mao3-21/+30
Add index entry for LoongArch system and do some small modification with LoongArch document with rst syntax. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-03-21host/include/loongarch64: Fix inline assembly compatibility with ClangYao Zi3-5/+7
Clang on LoongArch only accepts fp register names in the dollar-prefixed form, while GCC allows omitting the dollar. Change registers in ASM clobbers to the dollar-prefixed form to make user emulators buildable with Clang on loongarch64. No functional change invovled. Cc: qemu-stable@nongnu.org Fixes: adc8467e697 ("host/include/loongarch64: Add atomic16 load and store") Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
2025-03-20Merge tag 'pull-request-2025-03-19' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi10-53/+37
staging * Fix linking problem when CONFIG_VIRTIO_PCI is not set for s390x * Update functional tests parts of the documenation * Some minor fixes for functional tests # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmfawycRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbU2vA//UV2RdKVIQDS7MbMYRjmUr0NK9/9dLmrn # /lZVWXCBDEB7seu/VOGZmr1H0zoQ8XYJTSbrmp2cW0NRPhCVeAz9Zpg7+jt3Qy6/ # ahbiNQyhYztMbSa4XOOUEoLZBsfZILjWgqBilrRn7ng6wJoNabEIs/KqMP3O9qsx # TYCCnu5JkMF85Bf0l3kUJlLX0b5+BnpUNDke1cipvTa7u/Coz0mDBBZZtgW1bBj8 # TETuMC1JtCg3aj1ey7k0pK4nCd740mr5w659C4LE8NCE0/juc3AtRM5RCqU9tAGh # tXpfrZziyvSrAhyWieRQlgzLvrt2gTF/5FrqhPUssts+vkH1EgB56FiPXdqMtLRo # zU+SVRuOMHQZn7E6L9KQ7Gz5w98PSVGYxUUpWIvOx/0d9wgoIfYPjgtJz5UV11mV # Nnt304UV4FKw94V8S8JYUClamP4SMTMLZNRIsd46Ef+DOL1CI+jcDZBntijwSgs1 # 5fs0IZyl6ZXtmUibVWJ+PqyYW6YiAfi/wY/mJlfnvKVZjoudbhNkNOtC9hi4YTQd # yJ7gVy9A4OeQqXgiQcymFvlseggds7uPQ9/szuGC1RwrW2NYH1YLisKpNzPtqq16 # TEOnsozlDa9OUDshKxrA5rwHiDcSuqJjkP26N91AmdEQDgoQcbIKWghriTxkOV9Q # d2aJt+3KF04= # =cNi4 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Mar 2025 09:14:15 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-03-19' of https://gitlab.com/thuth/qemu: tests/functional/test_migration: Use "ncat" instead of "nc" in the exec test tests/functional/test_x86_64_kvm_xen: Remove avocado tags docs/devel/testing/functional: Add a section about logging docs/system/arm: Use "functional tests" instead of "integration tests" docs/system: Use the meson binary from the pyvenv tests/functional: remove all class level fields tests/functional/test_arm_orangepi: rename test class to 'OrangePiMachine' hw/virtio: Also include md stubs in case CONFIG_VIRTIO_PCI is not set Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-20Merge tag 'pull-riscv-to-apply-20250319' of ↵Stefan Hajnoczi14-143/+214
https://github.com/alistair23/qemu into staging Fourth RISC-V PR for 10.0 * Fix broken emulation link * Optimize the memory probing for vector fault-only-first loads * Fix access permission checks for CSR_SSP * Fixes a bug against `ssamoswap` behavior in M-mode * Fix IOMMU process directory table walk * Fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth() * Enhance VSTART and VL checks for vector instructions * Fix handling of cpu mask in riscv_hwprobe syscall * Add check for 16-bit aligned PC for different priv versions # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfaehkACgkQr3yVEwxT # gBOagRAAsSC/0Fof5EpXc14zmaw7CtoqSCTHVYXYxIEFjRu2Nj89z1HSlB00ptjZ # g/x5gxJRW8pGarYL6EAKKhk7BpswZ87DbsM/3kQwGraWN/or4SLj12E1V6+UhDi6 # e8qV3oHT8/dMoi/cUc9sM2FNah6gWckxy4QwLzX41jI6wkHe72IC52u9OP6b2ny5 # iky1ThDeQiZmGfj13se9cK1XFNPZgSnJFYD6k9OQTmaMzSShcM64ewv95RfiJbjA # s8kDmXYrrSQbjWyrjf2JIWhm6dFagFW4u/ho5481gZ1ntw1DnqlHXKCEWSPhIBOm # WzvfK0dEkmgtOW0DJ7aBdbDJWNRcYCW3xiuUlHrQ7QDRmwreTrF1mo9sD9KifwIo # NPzScf/O+GPuqDKcV6SfT6rV/Jpr8yaK9WaB/KeDsmhrmsDBn4GCrxu6Z/bLadCy # AnLItH8BCssSIA989VzwN0V3AsJK8cDQiRzM3/Mq8zp2yNvaBbuGLFxvAzV4sFZY # PIc7jhWek8Dw1SxIwuXvh/04iNkQNbnowzCQo7q7Cokf4vQtcTSuLblq3IgAJyDn # eCNXY0SgHNvA6DCxF+ZYAjpgo6ZFusGq1Yq9KzbaH+a3vYOOHhFix4wrFyyApu7+ # 1nBgETtewKfHqo2+GtYr/g1O+WYruf1TC5bCdiWpvvPDR/a7zJM= # =SqiB # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Mar 2025 04:02:33 EDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250319' of https://github.com/alistair23/qemu: target/riscv: Add check for 16-bit aligned PC for different priv versions. linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall target/riscv: fix handling of nop for vstart >= vl in some vector instruction target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth() hw/riscv/riscv-iommu: Fix process directory table walk target/riscv: fixes a bug against `ssamoswap` behavior in M-mode target/riscv: fix access permission checks for CSR_SSP optimize the memory probing for vector fault-only-first loads. docs/about/emulation: Fix broken link Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-20qdev, rust/hpet: fix type of HPET "timers" propertyPaolo Bonzini3-3/+41
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-20ppc/pnv: Fix system symbols in HOMER structure definitionsNicholas Piggin1-105/+96
These definitions were taken from skiboot firmware. I naively thought it would be nicer to keep the code similar by using the preprocessor, but it was pointed out that system headers might still use those symbols and cause something unexpected. Also just nicer to keep the QEMU tree clean. Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org> Cc: "Stefan Hajnoczi" <stefanha@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Fixes: 70bc5c2498f46 ("ppc/pnv: Make HOMER memory a RAM region") Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-20ppc/pnv: Move the PNOR LPC address into struct PnvPnorNicholas Piggin4-3/+6
Rather than use the hardcoded define throughout the tree for the PNOR LPC address, keep it within the PnvPnor object. This should solve a dead code issue in the BMC HIOMAP checks where Coverity (correctly) reported that the sanity checks are dead code. We would like to keep the sanity checks without turning them into a compile time assert in case we would like to make them configurable in future. Fixes: 4c84a0a4a6e5 ("ppc/pnv: Add a PNOR address and size sanity checks") Resolves: Coverity CID 1593723 Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-20ppc/spapr: Fix possible pa_features memory overflowNicholas Piggin1-0/+1
Coverity reports a possible memory overflow in spapr_dt_pa_features(). This should not be a true bug since DAWR1 cap is only be true for CPU_POWERPC_LOGICAL_3_10. Add an assertion to ensure any bug there is caught. Resolves: Coverity CID 1593722 Fixes: 5f361ea187ba ("ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine") Reviewed-By: Shivaprasad G Bhat <sbhat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-20ppc/xive2: Fix logical / bitwise comparison typoNicholas Piggin1-1/+1
The comparison as written is always false (perhaps confusingly, because the functions/macros are not really booleans but return 0 or the tested bit value). Change to use logical-and. Resolves: Coverity CID 1593721 Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-20pnv/xive: Fix possible undefined shift error in group size calculationNicholas Piggin2-8/+38
Coverity discovered a potential shift overflow in group size calculation in the case of a guest error. Add checks and logs to ensure a issues are caught. Make the group and crowd error checking code more similar to one another while here. Resolves: Coverity CID 1593724 Fixes: 9cb7f6ebed60 ("ppc/xive2: Support group-matching when looking for target") Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-20ppc/xive: Fix typo in crowd block level calculationNicholas Piggin1-1/+1
I introduced this bug when "tidying" the original patch, not Frederic. Paper bag for me. Fixes: 9cb7f6ebed60 ("ppc/xive2: Support group-matching when looking for target") Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-20rust: Kconfig: Factor out whether HPET is Rust or CPeter Maydell7-8/+11
Currently we require everywhere that wants to know if there is an HPET device to check for "CONFIG_HPET || CONFIG_X_HPET_RUST". Factor out whether the HPET device is Rust or C into a separate Kconfig stanza, so that CONFIG_HPET means "there is an HPET", and whether this has pulled in CONFIG_X_HPET_RUST or CONFIG_HPET_C is something the rest of QEMU can ignore. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Link: https://lore.kernel.org/r/20250319193110.1565578-3-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-20rust: Kconfig: Factor out whether PL011 is Rust or CPeter Maydell3-21/+17
Currently every board that uses the PL011 duplicates the logic that selects the Rust implementation if Rust was enabled and the C implementation if it does not. Factor this out into a separate Kconfig stanza, so that boards can go back to simply doing "select PL011" and get whichever implementation is correct for the build. This fixes a compilation failure if CONFIG_VMAPPLE is enabled in a Rust build, because hw/vmapple/Kconfig didn't have the "pick the Rust PL011 if Rust is enabled" logic in it. Fixes: 59f4d65584bd33 ("hw/vmapple/vmapple: Add vmapple machine type") Reported-by: Tanish Desai <tanishdesai37@gmail.com> Analyzed-by: Tanish Desai <tanishdesai37@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250319193110.1565578-2-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-20target/loongarch: Clean up virt_cpu_irq_init() error handlingBibo Mao1-3/+4
The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. virt_cpu_irq_init() is wrong that way: it passes &err to hotplug_handler_plug() twice. If both calls failed, this could trip error_setv()'s assertion. Moreover, if just one fails, the Error object leaks. Fortunately, these calls can't actually fail. Messed up in commit 50ebc3fc47f7 (hw/intc/loongarch_ipi: Notify ipi object when cpu is plugged) and commit 087a23a87c57 (hw/intc/loongarch_extioi: Use cpu plug notification). Clean this up by passing &error_abort instead. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250320032158.1762751-7-maobibo@loongson.cn> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2025-03-20target/loongarch: Remove unnecessary temporary variable assignmentBibo Mao1-3/+2
Temporary variable ret is assigned at last line and return, it can be removed and return directly. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250320032158.1762751-6-maobibo@loongson.cn> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2025-03-20hw/loongarch/virt: Eliminate error_propagate()Bibo Mao1-21/+11
When there is an error, it is put into a local variable and then propagated to somewhere else. Instead the error can be set right away, error propagation can be removed. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Message-ID: <20250320032158.1762751-5-maobibo@loongson.cn> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2025-03-20target/loongarch: Fix error handling of KVM feature checksBibo Mao1-2/+6
For some paravirt KVM features, if user forces to enable it however KVM does not support, qemu should fail to run and exit immediately, rather than continue to run. Here set error message and return directly in function kvm_arch_init_vcpu(). Fixes: 6edd2a9bec90 (target/loongarch/kvm: Implement LoongArch PMU extension) Fixes: 936c3f4d7916 (target/loongarch: Use auto method with LSX feature) Fixes: 5e360dabedb1 (target/loongarch: Use auto method with LASX feature) Fixes: 620d9bd0022e (target/loongarch: Add paravirt ipi feature detection) Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250320032158.1762751-2-maobibo@loongson.cn> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2025-03-20ppc/spapr: Fix RTAS stopped stateNicholas Piggin5-2/+30
This change takes the CPUPPCState 'quiesced' field added for powernv hardware CPU core controls (used to stop and start cores), and extends it to spapr to model the "RTAS stopped" state. This prevents the schedulers attempting to run stopped CPUs unexpectedly, which can cause hangs and possibly other unexpected behaviour. The detail of the problematic situation is this: A KVM spapr guest boots with all secondary CPUs defined to be in the "RTAS stopped" state. In this state, the CPU is only responsive to the start-cpu RTAS call. This behaviour is modeled in QEMU with the start_powered_off feature, which sets ->halted on secondary CPUs at boot. ->halted=true looks like an idle / sleep / power-save state which typically is responsive to asynchronous interrupts, but spapr clears wake-on-interrupt bits in the LPCR SPR. This more-or-less works. Commit e8291ec16da8 ("target/ppc: fix timebase register reset state") recently caused the decrementer to expire sooner at boot, causing a decrementer exception on secondary CPUs in RTAS stopped state. This was not a problem on TCG, but KVM limits how a guest can modify LPCR, in particular it prevents the clearing of wake-on-interrupt bits, and so in the course of CPU register synchronisation, the LPCR as set by spapr to model the RTAS stopped state is overwritten with KVM's LPCR value, and that then causes QEMU's interrupt code to notice the expired decrementer exception, turn that into an interrupt, and set CPU_INTERRUPT_HARD. That causes the CPU to be kicked, and the KVM vCPU thread to loop calling kvm_cpu_exec(). kvm_cpu_exec() calls kvm_arch_process_async_events(), which on ppc just returns ->halted. This is still true, so it returns immediately with EXCP_HLT, and the vCPU never goes to sleep because qemu_wait_io_event() sees CPU_INTERRUPT_HARD is set. All this while the vCPU holds the bql. This causes the boot CPU to eventually lock up when it needs the bql. So make 'quiesced' represent the "RTAS stopped" state, and have it explicitly not respond to exceptions (interrupt conditions) rather than rely on machine register state to model that state. This matches the powernv quiesced state very well because it essentially turns off the CPU core via a side-band control unit. There are still issues with QEMU and KVM idea of LPCR diverging and that is quite ugly and fragile that should be fixed. spapr should synchronize its LPCR properly with KVM, and not try to use values that KVM does not support. Reported-by: Misbah Anjum N <misanjum@linux.ibm.com> Tested-by: Misbah Anjum N <misanjum@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2025-03-19tests/functional/test_migration: Use "ncat" instead of "nc" in the exec testThomas Huth1-4/+3
"nc" can either be GNU netcat, OpenBSD netcat or NMap ncat. At least GNU netcat currently does not work with this test anymore, though the comment in the test says otherwise. GNU netcat seems to be quite unmaintained nowadays, according to its website (https://netcat.sourceforge.net/), the last public release is from 2004, so we should rather avoid that binary. In our CI, we are only using "ncat" in the containers (it's the only flavor that lcitool supports), thus to avoid silent regressions with the other netcats, let's limit this test to "ncat" only now. Reported-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Message-ID: <20250319105617.133191-1-thuth@redhat.com> Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19hw/xen: Downgrade a xen_bus_realize() non-error to warningMarkus Armbruster1-4/+3
xen_bus_realize() reports a failure to set up a watch as error, but it doesn't treat it as one: it simply continues. Report a warning instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250314143500.2449658-3-armbru@redhat.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2025-03-19hw/xen: Fix xen_bus_realize() error handlingMarkus Armbruster1-0/+1
The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. xen_bus_realize() is wrong that way: it passes &local_err to xs_node_watch() in a loop. If this fails in more than one iteration, it can trip error_setv()'s assertion. Fix by clearing @local_err. Fixes: c4583c8c394e (xen-bus: reduce scope of backend watch) Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250314143500.2449658-2-armbru@redhat.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2025-03-19target/riscv: Add check for 16-bit aligned PC for different priv versions.Yu-Ming Chang4-5/+27
For privilege version 1.12 or newer, C always implies Zca. We can only check ext_zca to allow 16-bit aligned PC addresses. For older privilege versions, we only check C. Signed-off-by: Yu-Ming Chang <yumin686@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <174184718265.10540.10120024221661781046-0@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19error: Strip trailing '\n' from an error string argumentMarkus Armbruster1-1/+1
Tracked down with scripts/coccinelle/err-bad-newline.cocci. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250312143504.1659061-1-armbru@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn>
2025-03-19cryptodev: Fix error handling in cryptodev_lkcf_execute_task()Markus Armbruster1-0/+3
When cryptodev_lkcf_set_op_desc() fails, we report an error, but continue anyway. This is wrong. We then pass a non-null @local_error to various functions, which could easily fail error_setv()'s assertion on failure. Fail the function instead. When qcrypto_akcipher_new() fails, we fail the function without reporting the error. This leaks the Error object. Add the missing error reporting. This also frees the Error object. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250312101131.1615777-1-armbru@redhat.com> Reviewed-by: zhenwei pi <pizhenwei@bytedance.com>
2025-03-19tests/functional/test_x86_64_kvm_xen: Remove avocado tagsThomas Huth1-28/+0
They have been forgotten to be removed when converting the test to the functional framework. Since they are of no use anymore, let's remove them now. Message-ID: <20250318171530.94966-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19docs/devel/testing/functional: Add a section about loggingThomas Huth1-2/+20
We should tell the users where to find the log file. While we're at it, also rename the "Overview" heading to a more accurate "Introduction to writing tests" instead. Reported-by: Aditya Gupta <adityag@linux.ibm.com> Message-ID: <20250318092021.53719-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscallRichard Henderson1-26/+29
The third argument of the syscall contains the size of the cpu mask in bytes, not bits. Nor is the size rounded up to a multiple of sizeof(abi_ulong). Cc: qemu-stable@nongnu.org Reported-by: Andreas Schwab <schwab@suse.de> Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250308225902.1208237-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19docs/system/arm: Use "functional tests" instead of "integration tests"Thomas Huth2-6/+6
We don't use the term "integration tests" for these kind of tests anymore, it's "functional tests" nowadays. Suggested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-ID: <20250318061420.20378-1-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19docs/system: Use the meson binary from the pyvenvThomas Huth3-4/+5
To avoid problems with the meson installation from the host system, we should always use the meson from our venv instead. Thus use this in the documentation, too. While we're at it, also mention that it has to be run from the build folder (in the igb.rst file; the other two files were already fine). Suggested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-ID: <20250318055415.16501-1-thuth@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19tests/functional: remove all class level fieldsDaniel P. Berrangé2-7/+0
A number of fields are set at the class level on QemuBaseTest, even though the exact same named field is then set at the object level later in most cases. The 'self.logger' initialization in ACPI bits test needs to be removed since 'self.log' won't exist at that point in the flow. It already initialized 'self.logger' later in the setUp() method, so the __init__ method was redundant. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20250317124300.84266-1-berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19tests/functional/test_arm_orangepi: rename test class to 'OrangePiMachine'Niek Linnenbank1-1/+1
The test class in this file contains all functional test cases for testing the Orange Pi PC board. It should be given a name matching the Qemu machine it covers. This commit sets the test class name to 'OrangePiMachine'. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Fixes: 380f7268b7b ("tests/functional: Convert the OrangePi tests to the functional framework") Message-ID: <20250316210232.46298-1-nieklinnenbank@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19hw/virtio: Also include md stubs in case CONFIG_VIRTIO_PCI is not setThomas Huth1-1/+2
For the s390x target, it's possible to build the QEMU binary without CONFIG_VIRTIO_PCI and only have the virtio-mem device via the ccw transport. In that case, QEMU currently fails to link correctly: /usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in function `s390_machine_device_pre_plug': ../hw/s390x/s390-virtio-ccw.c:579:(.text+0x1e96): undefined reference to `virtio_md_pci_pre_plug' /usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in function `s390_machine_device_plug': ../hw/s390x/s390-virtio-ccw.c:608:(.text+0x21a4): undefined reference to `virtio_md_pci_plug' /usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in function `s390_machine_device_unplug_request': ../hw/s390x/s390-virtio-ccw.c:622:(.text+0x2334): undefined reference to `virtio_md_pci_unplug_request' /usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in function `s390_machine_device_unplug': ../hw/s390x/s390-virtio-ccw.c:633:(.text+0x2436): undefined reference to `virtio_md_pci_unplug' clang: error: linker command failed with exit code 1 (use -v to see invocation) We also need to include the stubs when CONFIG_VIRTIO_PCI is missing. Fixes: aa910c20ec5 ("s390x: virtio-mem support") Message-ID: <20250313063522.1348288-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19target/riscv: fix handling of nop for vstart >= vl in some vector instructionChao Liu1-4/+14
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the instruction should be nop, but when I tested it, I found that QEMU will treat all elements as tail elements, and in the case of VTA=1, write all elements to 1. After troubleshooting, it was found that the vext_vx_rm_1 function was called in the vext_vx_rm_2, and then the vext_set_elems_1s function was called to process the tail element, but only VSTART >= vl was checked in the vext_vx_rm_1 function, which caused the tail element to still be processed even if it was returned in advance. So I've made the following change: Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 function, so that the VSTART register is checked correctly. Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when vstart >= vl") Signed-off-by: Chao Liu <lc00631@tecorigin.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <b2649f14915150be4c602d63cd3ea4adf47e9d75.1741573286.git.lc00631@tecorigin.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameterChao Liu4-60/+57
Some vector instructions are special, such as the vlm.v instruction, where setting its vl actually sets evl = (vl + 7) >> 3. To improve maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to check for the condition vstart >= vl. This function will also handle cases involving evl. Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when vstart >= vl") Signed-off-by: Chao Liu <lc00631@tecorigin.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <f575979874e323a9e0da7796aa391c7d87e56f88.1741573286.git.lc00631@tecorigin.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()Daniel Henrique Barboza1-1/+1
Coverity found the following issue: >>> CID 1593156: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "0x10 << depth" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 4299 depth = 16 << depth; Fix it by forcing the expression to be 64 bits wide by using '16ULL'. Resolves: Coverity CID 1593156 Fixes: c48bd18eae ("target/riscv: Add support for Control Transfer Records extension CSRs.") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250307124602.1905754-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19hw/riscv/riscv-iommu: Fix process directory table walkJason Chien2-3/+7
The PPN field in a non-leaf PDT entry is positioned differently from that in a leaf PDT entry. The original implementation incorrectly used the leaf entry's PPN mask to extract the PPN from a non-leaf entry, leading to an erroneous page table walk. This commit introduces new macros to properly define the fields for non-leaf PDT entries and corrects the page table walk. Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250301173751.9446-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19target/riscv: fixes a bug against `ssamoswap` behavior in M-modeDeepak Gupta1-0/+17
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds `ssamoswap` instruction. `ssamoswap` takes the code-point from existing reserved encoding (and not a zimop like other shadow stack instructions). If shadow stack is not enabled (via xenvcfg.SSE) and effective priv is less than M then `ssamoswap` must result in an illegal instruction exception. However if effective priv is M, then `ssamoswap` results in store/AMO access fault. See Section "22.2.3. Shadow Stack Memory Protection" of priv spec. Fixes: f06bfe3dc38c ("target/riscv: implement zicfiss instructions") Reported-by: Ved Shanbhogue <ved@rivosinc.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250306064636.452396-2-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19target/riscv: fix access permission checks for CSR_SSPDeepak Gupta1-0/+5
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But rather rules clearly specified in section "22.2.1. Shadow Stack Pointer (ssp) CSR access contr" in the priv spec. Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls for zicfiss". Thanks to Adam Zabrocki for bringing this to attention. Reported-by: Adam Zabrocki <azabrocki@nvidia.com> Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250306064636.452396-1-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19optimize the memory probing for vector fault-only-first loads.Paolo Savini1-45/+58
Fault-only-first loads in the RISC-V vector extension need to update the vl with the element index that causes an exception. In order to ensure this the emulation of this instruction used to probe the memory covered by the load operation with a loop that iterated over each element so that when a flag was raised it was possible to set the vl to the corresponding element index. This loop was executed every time whether an exception happened or not. This commit removes the per element memory probing from the main execution path and adds a broad memory probing first. If this probing raises any flag that is not a watchpoint flag (that per standard is allowed by this instruction) we proceed with the per element probing to find the index of the element causing the exception and set vl to such index. Signed-off-by: Paolo Savini <paolo.savini@embecosm.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250221155320.59159-2-paolo.savini@embecosm.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-19docs/about/emulation: Fix broken linkSantiago Monserrat Campanello1-1/+1
semihosting link to risc-v changed Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20250305102632.91376-1-santimonserr@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-03-18Update version for v10.0.0-rc0 releasev10.0.0-rc0Stefan Hajnoczi1-1/+1
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-17Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi4-11/+1
fixes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmfYLB4UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNp4Qf/U6yNnZ1I7yVwg7718TJBgOn3wyhI # 9wNGF6nPCqEOimZU+nzHXcdp7p+zvNCOdQdscZ2Sw+Ps3Sb6bCJ8wJFOxQdozq+W # QBH0s0/ni393XsZ7GoqgUBCh+SiaEVR+0oX8eGgxthnxFZ2IZG8qOl7kBw8ZPx3y # kMq08JF3jbotNMj0gK1MEK7SMM7aGp7z5vxnEIoo6qqfxVeACDmPMfyObxEVsCLx # GHu0mUfwoVSy1Azld81Q/fLgVqsuGulXqbfUvjw9a9yDdcB8p6ZlqsZyz1m7mqOO # 7eBzaJB4EiVPbfJb+Ybd4cmiUMM31RlXmI2vXMKTsgkoKUUnqFtyWbxMcg== # =dMFm # -----END PGP SIGNATURE----- # gpg: Signature made Mon 17 Mar 2025 10:05:18 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: Revert "meson.build: default to -gsplit-dwarf for debug info" hw/misc: use extract64 instead of 1 << i Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-17Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi1-0/+13
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEIV1G9IJGaJ7HfzVi7wSWWzmNYhEFAmfX5/cACgkQ7wSWWzmN # YhFRHQgArp4daHmnfc4r8TNel7fBjeSTpfDGwQcUJbcljKK2ABtylcESAEg6tsAw # aBzaZ2PwoTQfDV2s//g/d2uzd3BWH0Iu3qimsyBtx7Um7D4h7NsGB+gTB/7IhcK8 # 1LjMHqDnaeS6fzJ93/umTXuyQLzA3tIFkJBzvxVseLrmv6uBPmAy+PDNe/uZ2jeF # 2H20jNt/HMc1Yf7sE7NKTBkX+OxuIFkpOGcBtVxiPK1//Wmhw+v+zlQOFjUC+6CD # LxiBB0Q0tD7ekfbuF6x2SOnuzLDHgpMzgoGqLIYzeQhBX9TdHLM0LtEHHaMyW1pj # 7mGPSY4avVSM1sePgtmNJ5Y5r/xTRA== # =e7Sc # -----END PGP SIGNATURE----- # gpg: Signature made Mon 17 Mar 2025 05:14:31 EDT # gpg: using RSA key 215D46F48246689EC77F3562EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full] # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: vdpa: Allow vDPA to work on big-endian machine Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-17Revert "meson.build: default to -gsplit-dwarf for debug info"Paolo Bonzini3-10/+0
This reverts commit 563b1a35ed1f1151505d4fe5f723827d1b3fd4bc. Split debug info support is broken when cross compiling (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99973). People that would like to use it can add it via --extra-cflags. Reported-by: Konstantin Kostiuk <kkostiuk@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-17hw/misc: use extract64 instead of 1 << iTigran Sogomonian1-1/+1
1 << i is casted to uint64_t while bitwise and with val. So this value may become 0xffffffff80000000 but only 31th "start" bit is required. Use the bitfield extract() API instead. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Tigran Sogomonian <tsogomonian@astralinux.ru> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Link: https://lore.kernel.org/r/20241227104618.2526-1-tsogomonian@astralinux.ru Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-17vdpa: Allow vDPA to work on big-endian machineKonstantin Shkolnyy1-0/+13
Add .set_vnet_le() function that always returns success, assuming that vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and outputs the message: "backend does not support LE vnet headers; falling back on userspace virtio" Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Signed-off-by: Konstantin Shkolnyy <kshk@linux.ibm.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
generated by cgit v1.1 at 2025-04-06 16:20:01 +0000