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2014-06-10util/qemu-sockets.c: Avoid unused variable warningsPeter Maydell1-2/+1
The 'on' variable is never used, and 'off' is only used if IPV6_V6ONLY is defined; delete 'on' and move 'off' to the point where it is used. This avoids warnings from clang 3.4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10hw/sd/sd.c: Drop unused sd_acmd_type[] arrayPeter Maydell1-11/+0
Drop the sd_acmd_type[] array: it is never used. (The equivalent sd_cmd_type[] array for normal commands is used to identify those commands whose argument includes the card address in the top 16 bits; but for app commands the card address is passed with the APP_CMD prefix, not with the argument to the app command itself.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10hw/i386/pc.c: Remove unused parallel_io and parallel_irq variablesPeter Maydell1-3/+0
The variables parallel_io and parallel_irq are unused; delete them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10slirp: Remove unused zero_ethaddr[] variablePeter Maydell1-2/+0
The zero_ethaddr[] array is never used; delete it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10qtest: fix hex2nib for capital charactersSergey Fedorov1-1/+1
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10net: cadence_gem: Remove &desc[0] usagesPeter Crosthwaite1-2/+2
Just use desc instead. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10net: cadence_gem: Comment spelling sweepPeter Crosthwaite1-6/+6
Fix some typos in comments. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10net: cadence_gem: Add Tx descriptor fetch printfPeter Crosthwaite1-0/+3
Add a debug printf for TX descriptor fetching. This is helpful to anyone needing to debug TX ring buffer traversal. It is also now consistent with the RX code which has a similar printf. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10net: cadence_gem: Fix Tx descriptor updatePeter Crosthwaite1-5/+7
The local variable "desc" was being used to read-modify-write the first descriptor (of a multi-desc packet) upon packet completion. desc however continues to be used by the code as the current descriptor. Give this first desc RMW it's own local variable to avoid trampling. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-10Merge remote-tracking branch 'remotes/kraxel/tags/pull-console-20140610-1' ↵Peter Maydell1-13/+5
into staging console: two little bugfixes. # gpg: Signature made Tue 10 Jun 2014 12:01:07 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-console-20140610-1: console: fix -vga none -sdl crash console: kill MAX_CONSOLES, alloc consoles dynamically Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-10console: fix -vga none -sdl crashGerd Hoffmann1-4/+1
Call get_alloc_displaystate() for proper initialization instead of allocating with g_new(). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-06-10console: kill MAX_CONSOLES, alloc consoles dynamicallyGerd Hoffmann1-9/+4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-06-10Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20140610' into stagingPeter Maydell10-130/+560
Several patches for s390: - bugfixes: A fix for a long-standing bug in the css code as well as a fixup for the recent I/O adapter support. - Exploitation of the userspace cmma enablement/reset interface, if it is present. - Some debuggability improvements by logging unmanageable conditions. - virtio-ccw finally gets migration support for its structures. - Some cleanup as to how floating interrupts are injected. # gpg: Signature made Tue 10 Jun 2014 08:57:56 BST using RSA key ID C6F02FAF # gpg: Can't check signature: public key not found * remotes/cohuck/tags/s390x-20140610: s390x/kvm: inject via flic s390x: cleanup interrupt injection s390x/kvm: add alternative injection interface s390x: consolidate floating interrupts s390/virtio-ccw: migration support s390x/kvm: Log unmanageable program interruptions s390x/kvm: Log unmanageable external interruptions s390x/kvm: enable/reset cmma via vm attributes s390x/kvm: make flic play well with old kernels s390x/css: handle emw correctly for tsch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-10s390x/kvm: inject via flicCornelia Huck3-1/+29
Try to inject floating interrupts via the flic if it is available. This allows us to inject the full range of floating interrupts. Reviewed-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x: cleanup interrupt injectionCornelia Huck6-120/+91
Remove the need for a cpu to inject a floating interrupt on kvm. Acked-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x/kvm: add alternative injection interfaceCornelia Huck2-0/+88
Add kvm_s390_{vcpu,floating}_interrupt, which offer the possibility to inject interrupts with larger payloads (when a kvm backend becomes available). Moreover, kvm_s390_floating_interrupt() does no longer have the bogus requirement for a vcpu. Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x: consolidate floating interruptsCornelia Huck4-40/+52
Move the injection code for all floating interrupts to interrupt.c and add a comment. Also get rid of the #ifdef CONFIG_KVM for the service interrupt. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390/virtio-ccw: migration supportJens Freimann3-0/+208
This patch adds live migration support for virtio-ccw devices. It's not done with vmstate because virtio itself is not yet ported to vmstate either. Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x/kvm: Log unmanageable program interruptionsThomas Huth1-0/+6
The kernel only drops to userspace if an endless program interrupt loop has been detected. Let's print an error message in this case to inform the user about the crash and stop the affected CPU with a panic event, just like it is already done for the external interruption loop detection. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x/kvm: Log unmanageable external interruptionsThomas Huth1-6/+29
Interception code 0x14 only drops to userspace when an unmanageable external interruption interception occured (e.g. if the External New PSW does not disable external interruptions). Instead of bailing out via the default handler, it is better to inform the user with a proper error message that also includes the bad PSW, and to stop the affected CPU with a panic event instead. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x/kvm: enable/reset cmma via vm attributesDominik Dingel4-0/+76
Exploit the new api for userspace-controlled cmma. If supported, enable cmma during kvm initialization and register a reset handler for cmma, which is also called directly from the load IPL code. The reset functionality is needed to reset the cmma state of the guest pages, e.g. if a system reset is triggered via qemu monitor; otherwise this could result in data corruption. A guest triggered reboot may now lead to multiple cmma resets; this is OK, however, as this is slowpath anyway and the simplest way to achieve the intended effects. Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x/kvm: make flic play well with old kernelsCornelia Huck1-2/+4
If we run with an old kernel that does not support KVM_CAP_IRQ_ROUTING, we don't have to do anything in the ->register_io_adapter and ->io_adapter_map callbacks and therefore should return 0 instead of -ENOSYS (just as the non-kvm flic does). This fixes using adapter interrupts when running under an older kernel, which broke with "s390x: add I/O adapter registration". Reported-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-10s390x/css: handle emw correctly for tschCornelia Huck1-4/+20
We should not try to store the emw portion of the irb if extended measurements are not applicable. In particular, we should not surprise the guest by storing a larger irb if it did not enable extended measurements. Cc: qemu-stable@nongnu.org Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-06-09Merge remote-tracking branch ↵Peter Maydell14-127/+731
'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging ---------------------------------------------------------------- target-arm queue: * support -bios option in vexpress boards * register the Cortex-A57 impdef system registers * fix handling of UXN bit in ARMv8 page tables * complete support of crypto insns in A32/T32 * implement CRC and crypto insns in A64 * fix bugs in generic timer control register ---------------------------------------------------------------- # gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140609-1: target-arm: Delete unused iwmmxt_msadb helper target-arm: Fix errors in writes to generic timer control registers target-arm: A64: Implement two-register SHA instructions target-arm: A64: Implement 3-register SHA instructions target-arm: A64: Implement AES instructions target-arm: A32/T32: Mask CRC value in calling code, not helper target-arm: A64: Implement CRC instructions target-arm: VFPv4 implies half-precision extension target-arm: Clean up handling of ARMv8 optional feature bits target-arm: Remove unnecessary setting of feature bits target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 target-arm: A64: Use PMULL feature bit for PMULL target-arm: add support for v8 VMULL.P64 instruction target-arm: Allow 3reg_wide undefreq to encode more bad size options target-arm: add support for v8 SHA1 and SHA256 instructions target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables target-arm: Prepare cpreg writefns/readfns for EL3/SecExt target-arm/cpu64.c: Actually register Cortex-A57 impdef registers vexpress: Add support for the -bios flag to provide firmware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell21-263/+195
into staging Tracing pull request # gpg: Signature made Mon 09 Jun 2014 14:44:18 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/tracing-pull-request: trace: Replace fprintf with error_report and print location trace: Multi-backend tracing trace: Replace error with warning if event is not defined simpletrace: add support for trace record pid field trace: add pid field to simpletrace record Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell3-13/+0
The iwmmxt_msadb helper and its corresponding gen function are unused; delete them. (This function appears to have never been used right back to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq, and is presumably an accidental remnant from the initial development.) Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401822125-1822-1-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Fix errors in writes to generic timer control registersPeter Maydell1-3/+3
The code for handling writes to the generic timer control registers had several bugs: * ISTATUS (bit 2) is read-only but we forced it to zero on any write * the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where it should be '^' * the handling of IMASK was inverted: we should set the IRQ if ISTATUS is set and IMASK is clear, not if both are set The combination of these bugs meant that when running a Linux guest that uses the generic timers we would fairly quickly end up either forgetting that the timer output should be asserted, or failing to set the IRQ when the timer was unmasked. The result is that the guest never gets any more timer interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
2014-06-09target-arm: A64: Implement two-register SHA instructionsPeter Maydell2-1/+46
Implement the two-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-10-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement 3-register SHA instructionsPeter Maydell1-1/+58
Implement the 3-register SHA instruction group from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-9-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement AES instructionsPeter Maydell2-1/+51
Implement the AES instructions from the optional Crypto Extensions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-8-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell2-19/+16
Bring the 32-bit CRC helper functions into line with the A64 ones, by masking the high bytes of the value in the calling code rather than the helper. This is more efficient since we can determine the mask at translation time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-7-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Implement CRC instructionsPeter Maydell4-1/+86
Implement the optional A64 CRC instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-6-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: VFPv4 implies half-precision extensionPeter Maydell2-4/+1
VFPv4 implies the presence of the half-precision floating point extension (which is optional in VFPv3). Add this implied rule to arm_cpu_realizefn() and remove some no-longer-needed explicit setting of the bit in initfns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-5-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Clean up handling of ARMv8 optional feature bitsPeter Maydell2-4/+14
CRC and crypto are both optional v8 extensions, so FEATURE_V8 should not imply them. Instead we should set these bits in the initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-4-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Remove unnecessary setting of feature bitsPeter Maydell2-4/+0
FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so we don't need to set them explicitly in initfns which set the V8 feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-3-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64Peter Maydell1-3/+0
The arm_any_initfn() is used only for the 32-bit linux-user "cpu any", so it only gets called in builds where TARGET_AARCH64 is not defined. Remove the unreachable line which sets ARM_FEATURE_AARCH64. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-2-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: A64: Use PMULL feature bit for PMULLPeter Maydell2-2/+2
Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for the A64 PMULL, not the AES feature bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell8-33/+61
Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication instruction in the A32/T32 instruction sets; this is part of the v8 Crypto Extensions. To do this we have to move the neon_pmull_64_{lo,hi} helpers from helper-a64.c into neon_helper.c so they can be used by the AArch32 translator. Inspired-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-4-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell1-12/+12
The current undefreq field in the neon_3reg_wide handling allows us to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is no longer sufficient with the advent of 64-bit polynomial VMULL, which means we want to UNDEF if size == 1. Change the undefreq encoding to use separate bits for all of "UNDEF if size == 0", "UNDEF if size == 1" and "UNDEF if size == 2". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-3-git-send-email-peter.maydell@linaro.org
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel6-7/+349
This adds support for the SHA1 and SHA256 instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org [PMM: * rebase * fix bad indent * add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case * use g_assert_not_reached() * don't re-extract bit 6 for the 2-reg-misc encodings * set the ELF HWCAP2 bits for the new features ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: Correct handling of UXN bit in ARMv8 LPAE page tablesIan Campbell1-9/+8
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can just treat this bit as UXN whenever we are in v8 mode. Also correctly extract the upper attributes from the PTE entry, the v8 version tried to avoid extracting the CONTIG bit and ended up with the upper bits being off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG bit. This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f" seen when modprobing modules under Linux. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Claudio Fontana <claudio.fontana@huawei.com> Cc: Rob Herring <robherring2@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm: Prepare cpreg writefns/readfns for EL3/SecExtFabian Aggeler1-14/+14
This patch changes some readfns/writefns to use raw_write and raw_read functions, which use the fieldoffset specified in ARMCPRegInfo instead of directly accessing the field. This will simplify patches for EL3 & Security Extensions. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Message-id: 1401962428-14749-1-git-send-email-aggelerf@ethz.ch Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09target-arm/cpu64.c: Actually register Cortex-A57 impdef registersPeter Maydell1-0/+1
cpu64.c contains a reginfo list for the impdef registers on the Cortex-A57; however we forgot to actually call define_arm_cp_regs(), so it was sitting there doing nothing. Remedy this omission. Message-id: 1401226259-23121-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09vexpress: Add support for the -bios flag to provide firmwareGrant Likely1-0/+13
Right now to run firmware inside the QEMU VExpress model requires padding out the firmware image to the size of the virtual flash and passing it in via the -pflash argument. If the firmware image is passed without padding, then QEMU will fail. Also, when passed as a -pflash argument, QEMU treats the file as persistent storage and will modify the file. The -bios flag provides the semantics that we want for providing a firmware image. This patch maps the contents of the -bios file into the address space at the boot flash location. Tested with the vexpress-a15 model and the Tianocore port. Signed-off-by: Grant Likely <grant.likely@linaro.org> Tested-by: Roy Franz <roy.franz@linaro.org> [PMM: folded long line, removed stray \n from error message, use correct variable for printing image name, exit(1) rather than 0] Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into ↵Peter Maydell5-37/+117
staging Net patches # gpg: Signature made Mon 09 Jun 2014 14:41:34 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/net-pull-request: e1000: remove broken support for 82573L tests: e1000: test additional device IDs e1000: allow command-line selection of card model vmxnet3: fix msix vectors unuse net: xilinx_ethlite: Fix Rx-pong interrupt Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09trace: Replace fprintf with error_report and print locationAlexey Kardashevskiy1-13/+18
This replaces fprintf(stderr) with error_report. This moves local variables to the beginning of the function to comply with QEMU's coding style. Suggested-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09trace: Multi-backend tracingLluís Vilanova20-234/+153
Adds support to compile QEMU with multiple tracing backends at the same time. For example, you can compile QEMU with: $ ./configure --enable-trace-backends=ftrace,dtrace Where 'ftrace' can be handy for having an in-flight record of events, and 'dtrace' can be later used to extract more information from the system. This patch allows having both available without recompiling QEMU. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09trace: Replace error with warning if event is not definedAlexey Kardashevskiy1-7/+7
At the moment QEMU exits if trace point is not defined which makes a developer life harder if he has to switch between branches with different traces implemented. This replaces error+exit wit WARNING if the tracepoint does not exist or not traceable. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09simpletrace: add support for trace record pid fieldStefan Hajnoczi1-11/+15
Extract the pid field from the trace record and print it. Change the trace record tuple from: (event_num, timestamp, arg1, ..., arg6) to: (event_num, timestamp, pid, arg1, ..., arg6) Trace event methods now support 3 prototypes: 1. <event-name>(arg1, arg2, arg3) 2. <event-name>(timestamp, arg1, arg2, arg3) 3. <event-name>(timestamp, pid, arg1, arg2, arg3) Existing script continue to work without changes, they only know about prototypes 1 and 2. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-06-09trace: add pid field to simpletrace recordStefan Hajnoczi1-2/+6
It is useful to know the QEMU process ID when working with traces from multiple VMs. Although the trace filename may contain the pid, tools that aggregate traces or even trace globally need somewhere to record the pid. There is a reserved field in the trace event header struct that we can use. It is not necessary to bump the simpletrace file format version number because it has already been incremented for the QEMU 2.1 release cycle in commit "trace: [simple] Bump up log version number". Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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