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2017-10-17spapr_pci: fail gracefully with non-pseries machine typesGreg Kurz1-1/+11
QEMU currently crashes when the user tries to add an spapr-pci-host-bridge on a non-pseries machine: $ qemu-system-ppc64 -M ppce500 -device spapr-pci-host-bridge,index=1 hw/ppc/spapr_pci.c:1535:spapr_phb_realize: Object 0x1003dacae60 is not an instance of type spapr-machine Aborted (core dumped) The same thing happens with the deprecated but still available child type spapr-pci-vfio-host-bridge. Fix both by checking the machine type with object_dynamic_cast(). Reviewed-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17spapr: Correct RAM size calculation for HPT resizingDavid Gibson1-2/+2
In order to prevent the guest from forcing the allocation of large amounts of qemu memory (or host kernel memory, in the case of KVM HV), we limit the size of Hashed Page Table (HPT) it is allowed to allocated, based on its RAM size. However, the current calculation is not correct: it only adds up the size of plugged memory, ignoring the base memory size. This patch corrects it. While we're there, use get_plugged_memory_size() instead of directly calling pc_existing_dimms_capacity(). The only difference is that it will abort on failure, which is right: a failure here indicates something wrong within qemu. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Laurent Vivier <lvivier@redhat.com>
2017-10-17ppc: pnv: consolidate type definitions and batch register themIgor Mammedov1-58/+34
Use a new DEFINE_TYPES() helper to simplify type registration Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: drop PnvChipClass::cpu_model fieldIgor Mammedov4-19/+13
deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: define core types staticallyIgor Mammedov1-28/+20
pnv core type definition doesn't have any fields that require it to be defined at runtime. So replace code that fills in TypeInfo at runtime with static TypeInfo array that does the same at complie time. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: drop PnvCoreClass::cpu_oc fieldIgor Mammedov2-7/+12
deduce cpu type directly from core type instead of maintaining type mapping in PnvCoreClass::cpu_oc and doing extra cpu_model parsing in pnv_core_class_init() Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: normalize core/chip type namesIgor Mammedov4-6/+11
typically for cpus/core type names following convention is used new_type_prefix-superclass_typename make PNV core/chip to follow common convention. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: pnv: use generic cpu_model parsingIgor Mammedov3-17/+15
use common cpu_model prasing in vl.c and set default cpu_model using generic MachineClass::default_cpu_type. Beside of switching to generic infrastructure it solves several issues. * ppc_cpu_class_by_name() is used to deal with lower/upper case and alias translations into actual cpu type, which fixes '-M powernv -cpu power8' and '-M powernv -cpu power9_v1.0' usecases which error out with: 'invalid CPU model 'FOO' for powernv machine' * allows to switch to lower-case typenames in pnv chip/core name (by convention typnames should be lower-case) * replace aliased names /power8, power9, .../ with exact cpu model names (i.e. typenames should be stable but aliases might decide to point to other cpu model withi family or changed by kvm). It will also help to simplify pnv_chip/core code and get rid of dependency on cpu_model parsing. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [dwg: Updated to make DD2.0 as default POWER9 chip] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: use generic cpu_model parsingIgor Mammedov7-39/+24
use generic cpu_model parsing introduced by (6063d4c0f vl.c: convert cpu_model to cpu type and set of global properties before machine_init()) it allows to: * replace sPAPRMachineClass::tcg_default_cpu with MachineClass::default_cpu_type * drop cpu_parse_cpu_model() from hw/ppc/spapr.c and reuse one in vl.c * simplify spapr_get_cpu_core_type() by removing not needed anymore recurrsion since alias look up happens earlier at vl.c and spapr_get_cpu_core_type() works only with resulted from that cpu type. * spapr no more needs to parse/depend on being phased out MachineState::cpu_model, all tha parsing done by generic code and target specific callback. Signed-off-by: Igor Mammedov <imammedo@redhat.com> [dwg: Correct minor compile error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: move ppc_cpu_lookup_alias() before its first userIgor Mammedov1-13/+13
next commit will drop ppc_cpu_lookup_alias() declaration from header and make it static which will break its last user ppc_cpu_class_by_name() since ppc_cpu_class_by_name() defined before ppc_cpu_lookup_alias(). To avoid this move ppc_cpu_lookup_alias() right before ppc_cpu_class_by_name(). Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: use cpu model names as tcg defaults instead of aliasesIgor Mammedov1-2/+2
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: register 'host' core type along with the rest of core typesIgor Mammedov3-13/+4
consolidate 'host' core type registration by moving it from KVM specific code into spapr_cpu_core.c, similar like it's done in x86 target. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: use cpu type name directlyIgor Mammedov4-14/+10
replace sPAPRCPUCoreClass::cpu_class with cpu type name since it were needed just to get that at points it were accessed. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: define core types staticallyIgor Mammedov2-59/+30
spapr core type definition doesn't have any fields that require it to be defined at runtime. So replace code that fills in TypeInfo at runtime with static TypeInfo array that does the same at complie time. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: move '-cpu foo,compat=xxx' parsing into ppc_cpu_parse_featurestr()Igor Mammedov5-52/+59
there is a dedicated callback CPUClass::parse_features which purpose is to convert -cpu features into a set of global properties AND deal with compat/legacy features that couldn't be directly translated into CPU's properties. Create ppc variant of it (ppc_cpu_parse_featurestr) and move 'compat=val' handling from spapr_cpu_core.c into it. That removes a dependency of board/core code on cpu_model parsing and would let to reuse common -cpu parsing introduced by 6063d4c0 Set "max-cpu-compat" property only if it exists, in practice it should limit 'compat' hack to spapr machine and allow to avoid including machine/spapr headers in target/ppc/cpu.c Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model()Igor Mammedov3-32/+4
ppc_cpu_parse_features() is doing practically the same thing as generic cpu_parse_cpu_model(). So remove duplicated impl. and reuse generic one. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: 40p/prep: replace cpu_model with cpu_typeIgor Mammedov1-8/+4
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: virtex-ml507: replace cpu_model with cpu_typeIgor Mammedov1-7/+4
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: replace cpu_model with cpu_type on ref405ep,taihu boardsIgor Mammedov2-4/+6
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: bamboo: use generic cpu_model parsingIgor Mammedov1-5/+2
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: mac_oldworld: use generic cpu_model parsingIgor Mammedov1-4/+2
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: mac_newworld: use generic cpu_model parsingIgor Mammedov1-9/+6
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17ppc: mpc8544ds/e500plat: use generic cpu_model parsingIgor Mammedov3-7/+4
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17qom: add helper macro DEFINE_TYPES()Igor Mammedov1-0/+36
DEFINE_TYPES() will help to simplify following routine patterns: static void foo_register_types(void) { type_register_static(&foo1_type_info); type_register_static(&foo2_type_info); ... } type_init(foo_register_types) or static void foo_register_types(void) { int i; for (i = 0; i < ARRAY_SIZE(type_infos); i++) { type_register_static(&type_infos[i]); } } type_init(foo_register_types) with a single line DEFINE_TYPES(type_infos) where types have static definition which could be consolidated in a single array of TypeInfo structures. It saves us ~6-10LOC per use case and would help to replace imperative foo_register_types() there with declarative style of type registration. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17qom: introduce type_register_static_array()Igor Mammedov2-0/+19
it will help to remove code duplication of registration static types in places that have open coded loop to perform batch type registering. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17hw/ppc/spapr.c: abort unplug_request if previous unplug isn't doneDaniel Henrique Barboza1-2/+14
LMB removal is completed only when the spapr_lmb_release callback is called after all DRCs of the dimm are detached. During this time, it is possible that a unplug request for the same dimm arrives, trying to detach DRCs that were detached by the guest in the first unplug_request. BQL doesn't help in this case - the lock will prevent any concurrent removal from happening until the end of spapr_memory_unplug_request only. What happens is that the second unplug_request ends up calling spapr_drc_detach in a DRC that were detached already, causing an assert error in spapr_drc_detach (e.g https://bugs.launchpad.net/qemu/+bug/1718118). spapr_lmb_release uses a structure called sPAPRDIMMState, stored in the spapr->pending_dimm_unplugs QTAIL, to track how many LMB DRCs are left to be detached by the guest. When there are no more DRCs left, this structure is deleted and the pc-dimm unplug handler is called to finish the process. This patch reuses the sPAPRDIMMState to allow unplug_request to know if there is an ongoing unplug process for a given dimm, aborting the unplug request in this case, by doing the following changes: - in spapr_lmb_release callback, move the dimm state removal to the end, after pc-dimm unplug handler. With this change we can check for the existence of the dimm state to see if the unplug process is done. - use spapr_pending_dimm_unplugs_find in spapr_memory_unplug_request to check if the dimm state exists. If positive, there is an unplug operation already in progress for this dimm, meaning that we should abort it and warn the user about it. Fixes: https://bugs.launchpad.net/qemu/+bug/1718118 Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17target/ppc: Fix carry flag setting for shift algebraic instructionsSandipan Das2-8/+20
For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift right algebraic instructions whenever the CA bit is to be set. This change affects the following instructions: * Shift Right Algebraic Word (sraw[.]) * Shift Right Algebraic Word Immediate (srawi[.]) * Shift Right Algebraic Doubleword (srad[.]) * Shift Right Algebraic Doubleword Immediate (sradi[.]) Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17target/ppc: Add POWER9 DD2.0 model informationDavid Gibson3-2/+6
At the moment the only POWER9 model which is listed in qemu is v1.0 (aka "DD1"). This is a very early (read, buggy) version which will never be released to the public - it was included in qemu only for the convenience of those doing bringup on the early silicon. For bonus points, we actually had its PVR incorrect in the table (0x004e0000 instead of 0x004e0100). We also never actually implemented the differences in behaviour (read, bugs) that marked DD1 in qemu. Now that we know the PVR for the substantially better v2.0 (DD2) chip, include it and make it the default POWER9 in qemu. For the time being we leave the DD1 definition in place for the poor souls (read, me) who still need to work with DD1 hardware. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17spapr: sanity check size of the CAS bufferGreg Kurz1-0/+7
The CAS buffer is provided by SLOF. A broken SLOF could pass a silly size: either smaller than the diff header, in which case the current code will try to allocate 16 Exabytes of memory and g_malloc0() will abort, or bigger than the maximum memory provisioned for SLOF (ie, 40 Megabytes), which doesn't make sense. Both cases indicate that SLOF has a bug. Let's print out an explicit error message and exit since rebooting as we do with other errors would only result in a reset loop. Signed-off-by: Greg Kurz <groug@kaod.org> [dwg: Fix format specifier that broke 32-bit builds] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17spapr: fix OF word name in commentGreg Kurz1-1/+2
Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17target/ppc: Remove unused PPC 460 and 460F definitionsThomas Huth1-217/+0
We don't have any 460 or 460F CPUs in QEMU, so the init functions are just dead code. Let's simply remove them (translate_init.c is already big enough without them). Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17hw/ppc: use 0 instead of fdt_path_offset(fdt, "/")Greg Kurz2-4/+2
The offset of the root node is guaranteed to be 0. This doesn't fix anything, it's just trivial cleanup of the two remaining places where this was done under hw/ppc. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-17macio: add missing registers to VMStateDescriptionMark Cave-Ayland1-1/+3
Commit 4f7265f "ppc/ide/macio: Add missing registers" added two extra macio registers but forgot to add them to the corresponding VMStateDescription. The version number is bumped accordingly, although this will have little effect given that the Mac machines are practically unmigratable. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: John Snow <jsnow@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-10-16Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell100-159/+985
pc, pci, virtio: fixes, features A bunch of fixes all over the place. A new vmcore device - the user interface around it is still somewhat controversial, but I feel most of the code is fine, suggestions can be addressed by adding patches on top. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 15 Oct 2017 04:02:23 BST # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (26 commits) tests/pxe: Test more NICs when running in SPEED=slow mode pc: remove useless hot_add_cpu initialisation isapc: Remove unnecessary migration compatibility code virtio-pci: Replace modern_as with direct access to modern_bar virtio: fix descriptor counting in virtqueue_pop hw/gen_pcie_root_port: make IO RO 0 on IO disabled pci: Validate interfaces on base_class_init xen/pt: Mark TYPE_XEN_PT_DEVICE as hybrid pci: Add INTERFACE_CONVENTIONAL_PCI_DEVICE to Conventional PCI devices pci: Add INTERFACE_PCIE_DEVICE to all PCIe devices pci: Add interface names to hybrid PCI devices pci: conventional-pci-device and pci-express-device interfaces PCI: PCIe access should always be little endian virtio/pci/migration: Convert to VMState hw/pci-bridge/pcie_pci_bridge: properly handle MSI unavailability case pci: allow 32-bit PCI IO accesses to pass through the PCI bridge virtio/vhost: reset dev->log after syncing MAINTAINERS: add Dump maintainers scripts/dump-guest-memory.py: add vmcoreinfo kdump: set vmcoreinfo location ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-16Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-10-14' into ↵Peter Maydell7-96/+89
staging nbd patches for 2017-10-14 - Marc-André Lureau - NBD: use g_new() family of functions - Vladimir Sementsov-Ogievskiy - first half of 00/13 nbd minimal structured read # gpg: Signature made Sun 15 Oct 2017 01:38:47 BST # gpg: using RSA key 0xA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2017-10-14: nbd: header constants indenting nbd/server: simplify reply transmission nbd/server: refactor nbd_co_send_simple_reply parameters nbd/server: do not use NBDReply structure nbd/server: structurize simple reply header sending nbd: rename some simple-request related objects to be _simple_ block/nbd-client: refactor nbd_co_receive_reply block/nbd-client: assert qiov len once in nbd_co_request NBD: use g_new() family of functions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-16Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell4-20/+65
staging # gpg: Signature made Fri 13 Oct 2017 14:49:22 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: block/throttle.c: add bdrv_co_drain_begin/end callbacks block: rename bdrv_co_drain to bdrv_co_drain_begin block: add bdrv_co_drain_end callback Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-16Merge remote-tracking branch ↵Peter Maydell17-371/+1216
'remotes/stefanberger/tags/pull-tpm-2017-10-04-3' into staging Merge tpm 2017/10/04 v3 # gpg: Signature made Fri 13 Oct 2017 12:37:07 BST # gpg: using RSA key 0x75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * remotes/stefanberger/tags/pull-tpm-2017-10-04-3: specs: Describe the TPM support in QEMU tpm: Move tpm_cleanup() to right place tpm: Added support for TPM emulator tpm-passthrough: move reusable code to utils tpm-backend: Move realloc_buffer() implementation to tpm-tis model tpm-backend: Add new API to read backend TpmInfo tpm-backend: Made few interface methods optional tpm-backend: Initialize and free data members in it's own methods tpm-backend: Move thread handling inside TPMBackend tpm-backend: Remove unneeded member variable from backend class tpm: Use EMSGSIZE instead of EBADMSG to compile on OpenBSD Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-16Merge remote-tracking branch 'remotes/elmarco/tags/vu-pull-request' into stagingPeter Maydell3-7/+56
# gpg: Signature made Thu 12 Oct 2017 21:52:28 BST # gpg: using RSA key 0xDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/vu-pull-request: libvhost-user: Support VHOST_USER_SET_SLAVE_REQ_FD libvhost-user: Update and fix feature and request lists vhost-user-bridge: Only process received packets on started queues libvhost-user: vu_queue_started Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-15tests/pxe: Test more NICs when running in SPEED=slow modeThomas Huth1-10/+21
The pxe-test is a very good test to excercise NICs, thus we should use it to test all NICs that can be used by the BIOS for booting via network. However, to avoid that the default testing time increases too much, the additional NICs are only tested in the "make check SPEED=slow" mode. The virtio-net NIC on ppc64 is now also only tested in slow mode, since the test on ppc64 is really quite slow and we've got test coverage for virtio-net in big endian mode now on s390x, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pc: remove useless hot_add_cpu initialisationLaurent Vivier2-3/+0
Since 4458fb3a79 (pc: Eliminate pc_default_machine_options()), hot_add_cpu is set in pc_machine_class_init(), so we don't need to set it in pc_q35_machine_options(), pc_i440fx_machine_options() and xenfv_machine_options(), except to clear it in pc_i440fx_1_4_machine_opt(). Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15isapc: Remove unnecessary migration compatibility codeEduardo Habkost1-2/+0
We don't touch isapc when we change guest ABI and add new entries to PC_COMPAT_* or new PCMachineClass compat flags. This means isapc never guaranteed guest ABI and cross-QEMU-version live migration compatibility. There's no point in keeping code for kvm-pv-eoi and APIC ID compatibility in pc_init_isa(). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15virtio-pci: Replace modern_as with direct access to modern_barAlexey Kardashevskiy2-38/+54
The modern bar is accessed now via yet another address space created just for that purpose and it does not really need FlatView and dispatch tree as it has a single memory region so it is just a waste of memory. Things get even worse when there are dozens or hundreds of virtio-pci devices - since these address spaces are global, changing any of them triggers rebuilding all address spaces. This replaces indirect accesses to the modern BAR with a simple lookup and direct calls to memory_region_dispatch_read/write. This is expected to save lots of memory at boot time after applying: [Qemu-devel] [PULL 00/32] Misc changes for 2017-09-22 Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15virtio: fix descriptor counting in virtqueue_popWolfgang Bumiller1-3/+3
While changing the s/g list allocation, commit 3b3b0628 also changed the descriptor counting to count iovec entries as split by cpu_physical_memory_map(). Previously only the actual descriptor entries were counted and the split into the iovec happened afterwards in virtqueue_map(). Count the entries again instead to avoid erroneous "Looped descriptor" errors. Reported-by: Hans Middelhoek <h.middelhoek@ospito.nl> Link: https://forum.proxmox.com/threads/vm-crash-with-memory-hotplug.35904/ Fixes: 3b3b0628217e ("virtio: slim down allocation of VirtQueueElements") Signed-off-by: Wolfgang Bumiller <w.bumiller@proxmox.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15hw/gen_pcie_root_port: make IO RO 0 on IO disabledMarcel Apfelbaum1-0/+7
IO_LIMIT and IO_BASE registers should not be writable if gen_pcie_root_port's io-reserve property is set to 0. The COMMAND register should have the IO flag read only. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: Validate interfaces on base_class_initEduardo Habkost1-0/+12
Make sure we don't forget to add the Conventional PCI or PCI Express interface names on PCI device classes in the future. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Revieed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15xen/pt: Mark TYPE_XEN_PT_DEVICE as hybridEduardo Habkost1-0/+1
xen-pt doesn't set the is_express field, but is supposed to be able to handle PCI Express devices too. Mark it as hybrid. Suggested-by: Jan Beulich <JBeulich@suse.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: Add INTERFACE_CONVENTIONAL_PCI_DEVICE to Conventional PCI devicesEduardo Habkost64-0/+296
Add INTERFACE_CONVENTIONAL_PCI_DEVICE to all direct subtypes of TYPE_PCI_DEVICE, except: 1) The ones that already have INTERFACE_PCIE_DEVICE set: * base-xhci * e1000e * nvme * pvscsi * vfio-pci * virtio-pci * vmxnet3 2) base-pci-bridge Not all PCI bridges are Conventional PCI devices, so INTERFACE_CONVENTIONAL_PCI_DEVICE is added only to the subtypes that are actually Conventional PCI: * dec-21154-p2p-bridge * i82801b11-bridge * pbm-bridge * pci-bridge The direct subtypes of base-pci-bridge not touched by this patch are: * xilinx-pcie-root: Already marked as PCIe-only. * pcie-pci-bridge: Already marked as PCIe-only. * pcie-port: all non-abstract subtypes of pcie-port are already marked as PCIe-only devices. 3) megasas-base Not all megasas devices are Conventional PCI devices, so the interface names are added to the subclasses registered by megasas_register_types(), according to information in the megasas_devices[] array. "megasas-gen2" already implements INTERFACE_PCIE_DEVICE, so add INTERFACE_CONVENTIONAL_PCI_DEVICE only to "megasas". Acked-by: Alberto Garcia <berto@igalia.com> Acked-by: John Snow <jsnow@redhat.com> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: Add INTERFACE_PCIE_DEVICE to all PCIe devicesEduardo Habkost8-0/+31
Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE. Cc: Keith Busch <keith.busch@intel.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Max Reitz <mreitz@redhat.com> Cc: Dmitry Fleytman <dmitry@daynix.com> Cc: Jason Wang <jasowang@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Hannes Reinecke <hare@suse.com> Cc: qemu-block@nongnu.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: Add interface names to hybrid PCI devicesEduardo Habkost5-0/+22
The following devices support both PCI Express and Conventional PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag and/or conditional pcie_endpoint_cap_init() calls: * vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device()) * vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize()) * pvscsi (is_express=0, but PCIe handled by pvscsi_realize()) * virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize()) * base-xhci (is_express=1, but pcie_endpoint_cap_init() call is conditional on pci_bus_is_express(dev->bus) * Note that xhci does not clear QEMU_PCI_CAP_EXPRESS like the other hybrid devices Cc: Dmitry Fleytman <dmitry@daynix.com> Cc: Jason Wang <jasowang@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: conventional-pci-device and pci-express-device interfacesEduardo Habkost2-0/+18
Those two interfaces will be used to indicate which device types support Conventional PCI or PCI Express buses. Management software will be able to use the qom-list-types QMP command to query that information. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.1 at 2025-01-14 11:34:38 +0000