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2021-02-25scsi-disk: pass SCSI status to scsi_handle_rw_errorPaolo Bonzini1-11/+27
Instead of fishing it from *r->status, just pass the SCSI status as a positive value of the second parameter and an errno as a negative value. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi: introduce scsi_sense_from_errno()Paolo Bonzini3-47/+51
The new function is an extension of the switch statement in scsi-disk.c which also includes the errno cases only found in sg_io_sense_from_errno. This allows us to consolidate the errno handling. Extracted from a patch by Hannes Reinecke <hare@suse.de>. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi-disk: do not complete requests early for rerror/werror=ignorePaolo Bonzini1-2/+1
When requested to ignore errors, just do nothing and let the request complete normally. This means that the request will be accounted correctly. This is what commit 40dce4ee61 ("scsi-disk: fix rerror/werror=ignore", 2018-10-19) was supposed to do: Fixes: 40dce4ee61 ("scsi-disk: fix rerror/werror=ignore", 2018-10-19) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi-disk: move scsi_handle_rw_error earlierPaolo Bonzini1-85/+83
Remove the forward declaration. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25virtio-scsi: don't process IO on fenced dataplaneMaxim Levitsky1-9/+15
If virtio_scsi_dataplane_start fails, there is a small window when it drops the aio lock (in aio_wait_bh_oneshot) and the dataplane's AIO handler can still run during that window. This is done after the dataplane was marked as fenced, thus we use this flag to avoid it doing any IO. Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com> Message-Id: <20201217150040.906961-2-mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi: allow user to set werror as reportZihao Chang1-1/+2
'enospc' is the default for -drive, but qemu allows user to set drive option werror. If werror of scsi-generic is set to 'report' by user, qemu will not allow vm to start. This patch allow user to set werror as 'report' for scsi-generic. Signed-off-by: Zihao Chang <changzihao1@huawei.com> Reviewed-by: Fam Zheng <fam@euphon.net> Message-Id: <20201103061240.1364-1-changzihao1@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi: add tracing for SG_IO commandsHannes Reinecke3-2/+13
Add tracepoints for SG_IO commands to allow for debugging of SG_IO commands. Signed-off-by: Hannes Reinecke <hare@suse.de> Message-Id: <20201116183114.55703-4-hare@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25scsi: make io_timeout configurableHannes Reinecke3-9/+18
The current code sets an infinite timeout on SG_IO requests, causing the guest to stall if the host experiences a frame loss. This patch adds an 'io_timeout' parameter for SCSIDevice to make the SG_IO timeout configurable, and also shortens the default timeout to 30 seconds to avoid infinite stalls. Signed-off-by: Hannes Reinecke <hare@suse.de> Message-Id: <20201116183114.55703-3-hare@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25multiprocess: move feature to meson_options.txtPaolo Bonzini3-11/+14
While at it, improve the description of the feature in the summary and help message. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25configure: fix --enable-fuzzing linker failuresAlexander Bulekov1-0/+10
With --enable-fuzzing, QEMU_CFLAGS include -fsanitize=fuzzer-no-link. This should allow us to build non-fuzzer binaries using objects instrumented for fuzzing. However, to do that, we also need to link with -fsanitize=fuzzer-no-link. We were not doing that. Reported-by: Li Qiang <liq3ea@163.com>, Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Message-Id: <20210221174510.22542-1-alxndr@bu.edu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-25hvf: Sign the code after installationAkihiko Odaki2-7/+22
Before this change, the code signed during the build was installed directly. However, the signature gets invalidated because meson modifies the code to fix dynamic library install names during the install process. It also prevents meson to strip the code because the pre-signed file is not marked as an executable (although it is somehow able to perform the modification described above). With this change, the unsigned code will be installed and modified by meson first, and a script signs it later. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <20210225000614.46919-1-akihiko.odaki@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-21Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210221' into ↵Peter Maydell21-420/+710
staging MIPS patches queue - Drop redundant struct MemmapEntry (Bin) - Fix for Coverity CID 1438965 and 1438967 (Jiaxun) - Add MIPS bootloader API (Jiaxun) - Use MIPS bootloader API on fuloong2e and boston machines (Jiaxun) - Add PMON test for Loongson-3A1000 CPU (Jiaxun) - Convert to translator API (Philippe) - MMU cleanups (Philippe) - Promote 128-bit multimedia registers as global ones (Philippe) - Various cleanups/fixes on the VT82C686B southbridge (Zoltan) # gpg: Signature made Sun 21 Feb 2021 18:43:57 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/mips-20210221: (43 commits) vt82c686: Fix superio_cfg_{read,write}() functions vt82c686: Log superio_cfg unimplemented accesses vt82c686: Simplify by returning earlier vt82c686: Reduce indentation by returning early vt82c686: Remove index field of SuperIOConfig vt82c686: Move creation of ISA devices to the ISA bridge vt82c686: Simplify vt82c686b_realize() vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it vt82c686: Set user_creatable=false for VT82C686B_PM vt82c686: Fix up power management io base and config vt82c686: Correctly reset all registers to default values on reset vt82c686: Correct vt82c686-pm I/O size vt82c686: Make vt82c686-pm an I/O tracing region vt82c686: Fix SMBus IO base and configuration registers vt82c686: Reorganise code vt82c686: Move superio memory region to SuperIOConfig struct target/mips: Use GPR move functions in gen_HILO1_tx79() target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers target/mips: Rename 128-bit upper halve GPR registers target/mips: Promote 128-bit multimedia registers as global ones ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-21vt82c686: Fix superio_cfg_{read,write}() functionsBALATON Zoltan1-5/+6
These functions are memory region callbacks so we have to check against relative address not the mapped address. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch in 5, this is part 5/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Log superio_cfg unimplemented accessesBALATON Zoltan1-0/+3
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch in 5, this is part 4/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Simplify by returning earlierBALATON Zoltan1-6/+3
By returning earlier we can remove the 'can_write' boolean variable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch in 5, this is part 3/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Reduce indentation by returning earlyBALATON Zoltan1-24/+23
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split patch original in 5, this is part 2/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Remove index field of SuperIOConfigBALATON Zoltan1-7/+14
Remove the separate index value from SuperIOConfig and store the index at reg 0 which is reserved and returns 0 on read. This simplifies the object state. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch in 5, this is part 1/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Move creation of ISA devices to the ISA bridgeBALATON Zoltan2-24/+25
Currently the ISA devices that are part of the VIA south bridge, superio chip are wired up by board code. Move creation of these ISA devices to the VIA ISA bridge model so that board code does not need to access ISA bus. This also allows vt82c686b-superio to be made internal to vt82c686 which allows implementing its configuration via registers in subseqent commits. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <bf9400cc8e4ddd3129aa5678de4d3cf38384805f.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Simplify vt82c686b_realize()BALATON Zoltan1-14/+6
Remove unneeded variables and setting value to 0 on zero initialised data and replace check for error with error_fatal. Rationalise loop that sets PCI config header fields read only. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <e4caf35ca10a68f5c74ae3f93fa0bcfa9457beea.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on itBALATON Zoltan3-29/+59
The vt82c686b-pm model can be shared between VT82C686B and VT8231. The only difference between the two is the device id in what we emulate so make an abstract via-pm model by renaming appropriately and add types for vt82c686b-pm and vt8231-pm based on it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <34969fc7be984fa070479bfb9f748993a0aef31b.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Set user_creatable=false for VT82C686B_PMBALATON Zoltan1-1/+2
This device is part of the multifunction VIA superio/south bridge chip so not useful in itself. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <d0a806fed5e8055aee4fcf5b2f4790e6dd0f9dc6.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Fix up power management io base and configBALATON Zoltan1-10/+12
Similar to the SMBus io registers there is a power management io range that is set via similar base address reg and enable bit. Some handling of this was already there but with several problems: using the wrong registers and bits, wrong size range, not acually updating mapping and handling reset correctly, nor emulating any of the actual io registers. Some of these errors are fixed up here. After this patch we use the correct base address register, enable bit and region size and allow guests to map/unmap this region, but we still don't emulate any of the registers in this range. PMD notes regarding the Configuration Space Power Management Registers: - 0x40 General Configuration 0 - 0x41 General Configuration 1 . Bit 7: I/O Enable for ACPI I/O Base - 0x48 Power Mgmt I/O Base . Bit 0: Always set . Bits 7-15: Power Management I/O Register Base Address (this explains the change 0xffc0 -> 0xff80) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch, this is part 4/4, added notes] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Correctly reset all registers to default values on resetBALATON Zoltan1-4/+4
Reset the registers in the DeviceReset() handler which is called on each device reset, not in DeviceRealize() which is called once. Bit 0 of 'Power Mgmt I/O Base' register (offset 0x48) is always set. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Split original patch, this is part 3/4 (move to reset), document] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Correct vt82c686-pm I/O sizeBALATON Zoltan1-1/+1
Section "Offset 4B-48 – Power Management I/O Base" describes: Port Address for the base of the 128-byte Power Management I/O Register block. Correct the vt82c686-pm I/O region size. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch, this is part 2/4, reduced size to 128B] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Make vt82c686-pm an I/O tracing regionBALATON Zoltan2-2/+26
Previously just an empty RAM region was mapped on realize, now we add an empty io range logging access instead. I think the pm timer should be hooked up here but not sure guests need it. PMON on fuloong2e sets a base address but does not seem to enable region; the pegasos2 firmware pokes some regs but continues anyway so don't know if anything would make use of these facilities. Therefore this is just a clean up of previous state for now and not intending to fully implement missing functionality which could be done later if some guests need it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu> [PMD: Split original patch, this is part 1/4 (make 'vt82c686-pm' an I/O tracing region)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Fix SMBus IO base and configuration registersBALATON Zoltan2-16/+37
The base address of the SMBus io ports and its enabled status is set by registers in the PCI config space but this was not correctly emulated. Instead the SMBus registers were mapped on realize to the base address set by a property to the address expected by fuloong2e firmware. Fix the base and config register handling to more closely model hardware which allows to remove the property and allows the guest to control this mapping. Do all this in reset instead of realize so it's correctly updated on reset. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <f2ca2ad5f08ba8cee07afd9d67b4e75cda21db09.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Reorganise codeBALATON Zoltan1-139/+140
Move lines around so that object definitions become consecutive and not scattered around. This brings functions belonging to an object together so it's clearer what is defined and what parts belong to which object. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <9f942989dba46fc1c23b881f6cb135948f818c2f.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21vt82c686: Move superio memory region to SuperIOConfig structBALATON Zoltan1-8/+8
The superio memory region holds the io space index/data registers used to access the superio config registers that are implemented in struct SuperIOConfig. To keep these related things together move the memory region to SuperIOConfig and rename it accordingly. Also remove the unused "data" member of SuperIOConfig which is not needed as we store actual data values in the regs array. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <dc3c4e7632716ca73c10506bd02ee93b39c28705.1610223397.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Use GPR move functions in gen_HILO1_tx79()Philippe Mathieu-Daudé1-17/+4
We have handy functions to access GPR. Use gen_store_gpr() for Move From HI/LO Register and gen_load_gpr() for Move To opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-8-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé2-0/+22
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-7-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé1-1/+3
TCG displays the upper halve registers with the same name as their lower halves. Rename the upper halves with the '[hi]' suffix. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-6-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé3-27/+34
The cpu::mmr[] array contains the upper halves of 128-bit GPR registers. While they are only used by the R5900 CPU, the concept is generic and could be used by another MIPS implementation. Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global. When the code is similar to the GPR lower halves, move it close by. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-5-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé2-1/+2
We will access the cpu_HI/LO registers outside of translate.c. Make them publicly accessible. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-4-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Include missing "tcg/tcg.h" headerPhilippe Mathieu-Daudé1-0/+1
Commit 83be6b54123 ("Fix MSA instructions LD.<B|H|W|D> on big endian host") introduced use of typedef/prototypes declared in "tcg/tcg.h" without including it. This was not a problem because "tcg/tcg.h" is pulled in by "exec/cpu_ldst.h". To be able to remove this header there, we first need to include it here in op_helper.c, else we get: [222/337] Compiling C object libqemu-mips-softmmu.fa.p/target_mips_msa_helper.c.o target/mips/msa_helper.c: In function ‘helper_msa_ld_b’: target/mips/msa_helper.c:8214:9: error: unknown type name ‘TCGMemOpIdx’ 8214 | TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \ | ^~~~~~~~~~~ target/mips/msa_helper.c:8224:5: note: in expansion of macro ‘MEMOP_IDX’ 8224 | MEMOP_IDX(DF_BYTE) | ^~~~~~~~~ target/mips/msa_helper.c:8214:26: error: implicit declaration of function ‘make_memop_idx’ [-Werror=implicit-function-declaration] 8214 | TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \ | ^~~~~~~~~~~~~~ target/mips/msa_helper.c:8227:18: error: implicit declaration of function ‘helper_ret_ldub_mmu’ [-Werror=implicit-function-declaration] 8227 | pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC()); | ^~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210207232310.2505283-4-f4bug@amsat.org>
2021-02-21target/mips: Remove unused 'rw' argument from page_table_walk_refill()Philippe Mathieu-Daudé1-3/+3
As the 'rw' argument is unused, remove it. Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210220202026.2305667-1-f4bug@amsat.org>
2021-02-21target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessTypePhilippe Mathieu-Daudé2-10/+10
get_seg_physical_address() calls CPUMIPSTLBContext::map_address() handlers passing a MMUAccessType type. Update the prototype handlers to take a MMUAccessType argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-14-f4bug@amsat.org>
2021-02-21target/mips: Let get_seg*_physical_address() take MMUAccessType argPhilippe Mathieu-Daudé1-5/+6
get_physical_address() calls get_seg_physical_address() and get_segctl_physical_address() passing a MMUAccessType type. Let the prototypes use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-13-f4bug@amsat.org>
2021-02-21target/mips: Let get_physical_address() take MMUAccessType argumentPhilippe Mathieu-Daudé1-10/+10
All these functions: - mips_cpu_get_phys_page_debug() - cpu_mips_translate_address() - mips_cpu_tlb_fill() - page_table_walk_refill() - walk_directory() call get_physical_address() passing a MMUAccessType type. Let the prototype use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-12-f4bug@amsat.org>
2021-02-21target/mips: Let raise_mmu_exception() take MMUAccessType argumentPhilippe Mathieu-Daudé1-5/+5
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass MMUAccessType to raise_mmu_exception(). Let the prototype use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-11-f4bug@amsat.org>
2021-02-21target/mips: Let cpu_mips_translate_address() take MMUAccessType argPhilippe Mathieu-Daudé2-4/+4
The single caller, do_translate_address(), passes MMUAccessType to cpu_mips_translate_address(). Let the prototype use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-10-f4bug@amsat.org>
2021-02-21target/mips: Let do_translate_address() take MMUAccessType argumentPhilippe Mathieu-Daudé1-3/+4
The single caller, HELPER_LD_ATOMIC(), passes MMUAccessType to do_translate_address(). Let the prototype use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-9-f4bug@amsat.org>
2021-02-21target/mips: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2-2/+2
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-7-f4bug@amsat.org>
2021-02-21target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé1-16/+0
Remove these confusing and unused definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-6-f4bug@amsat.org>
2021-02-21target/mips: Remove access_type argument from get_physical_address()Philippe Mathieu-Daudé1-13/+9
get_physical_address() doesn't use the 'access_type' argument, remove it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-5-f4bug@amsat.org>
2021-02-21target/mips: Remove access_type arg from get_segctl_physical_address()Philippe Mathieu-Daudé1-10/+10
get_segctl_physical_address() doesn't use the 'access_type' argument, remove it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-4-f4bug@amsat.org>
2021-02-21target/mips: Remove access_type argument from get_seg_physical_addressPhilippe Mathieu-Daudé1-3/+3
get_seg_physical_address() doesn't use the 'access_type' argument, remove it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-3-f4bug@amsat.org>
2021-02-21target/mips: Remove access_type argument from map_address() handlerPhilippe Mathieu-Daudé2-12/+11
TLB map_address() handlers don't use the 'access_type' argument, remove it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-2-f4bug@amsat.org>
2021-02-21target/mips: fetch code with translator_ldPhilippe Mathieu-Daudé1-10/+10
Similarly to commits ae82adc8e29..7f93879e444, use the translator_ld*() API introduced in commit 409c1a0bf0f to fetch the code on the MIPS target. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210125105818.2707067-1-f4bug@amsat.org>
2021-02-21tests/acceptance: Test PMON with Loongson-3A1000 CPUJiaxun Yang2-0/+40
Test booting of PMON bootloader on loongson3-virt platform. $ (venv) AVOCADO_ALLOW_UNTRUSTED_CODE=1 \ avocado --show=app,console \ run -t machine:loongson3-virt tests/acceptance Fetching asset from tests/acceptance/machine_mips_loongson3v.py:MipsLoongson3v.test_pmon_serial_console JOB ID : 8e202b3727847c9104d0d3d6546ed225d35f6706 JOB LOG : /home/flygoat/avocado/job-results/job-2021-01-12T10.02-8e202b3/job.log (1/1) tests/acceptance/machine_mips_loongson3v.py:MipsLoongson3v.test_pmon_serial_console: console: PMON2000 MIPS Initializing. Standby... console: 00000000Jump to 9fc console: Init Memory done. console: The uncache data is: console: 00000000: 5555555555555555 console: 00000008: aaaaaaaaaaaaaaaa console: 00000010: 3333333333333333 console: 00000018: cccccccccccccccc console: 00000020: 7777777777777777 console: 00000028: 8888888888888888 console: 00000030: 1111111111111111 console: 00000038: eeeeeeeeeeeeeeee console: The cached data is: console: 00000000: 5555555555555555 console: 00000008: aaaaaaaaaaaaaaaa console: 00000010: 3333333333333333 console: 00000018: cccccccccccccccc console: 00000020: 7777777777777777 console: 00000028: 8888888888888888 console: 00000030: 1111111111111111 console: 00000038: eeeeeeeeeeeeeeee console: Copy PMON to execute location... console: start = 0x8f900000 console: s0 = 0x30300000 console: _edata = 0x8f989010 console: _end = 0x8f98a028copy text section done. console: Copy PMON to execute location done. console: sp=8f8fc000 console: Uncompressing Bios............................................................................OK,Booting Bios console: FREQ console: DONE console: DEVI console: ENVI console: MAPV console: NVRAM@8f7ff898 console: STDV console: 80100000: memory between 8f7ff400-8f800000 is already been allocated,heap is already above this point console: SBDD console: P12PCIH console: PCIH console: PCID console: setting up 1 bus console: PCI bus 0 slot 1: probe...completed console: PCI bus 0 slot 1/0: vendor/product: 0x106b/0x003f (serialbus, USB, interface: 0x10, revision: 0x00) console: PCI bus 0 slot 1/0: reg 0x10 = 0xffffff00 console: PCI bus 0 slot 2: probe...completed console: PCI bus 0 slot 2/0: vendor/product: 0x1af4/0x1000 (network, ethernet, interface: 0x00, revision: 0x00) console: PCI bus 0 slot 2/0: reg 0x10 = 0xffffffe1 console: PCI bus 0 slot 2/0: reg 0x14 = 0xfffff000 console: PCI bus 0 slot 2/0: reg 0x20 = 0xffffc00c console: PCI bus 0 slot 2/0: reg 0x30 = 0xfffc0000 console: PCI bus 0 slot 3: probe...completed console: PCI bus 0 slot 4: probe...completed console: PCI bus 0 slot 5: probe...completed console: PCI bus 0 slot 6: probe...completed console: PCI bus 0 slot 7: probe...completed console: PCI bus 0 slot 8: probe...completed console: PCI bus 0 slot 9: probe...completed console: PCI bus 0 slot 10: probe...completed console: PCI bus 0 slot 11: probe...completed console: PCI bus 0 slot 12: probe...completed console: PCI bus 0 slot 13: probe...completed console: PCI bus 0 slot 14: probe...completed console: PCI bus 0 slot 15: probe...completed console: PCI bus 0 slot 16: probe...completed console: PCI bus 0 slot 17: probe...completed console: PCI bus 0 slot 18: probe...completed console: PCI bus 0 slot 19: probe...completed console: PCI bus 0 slot 20: probe...completed console: PCI bus 0 slot 21: probe...completed console: PCI bus 0 slot 22: probe...completed console: PCI bus 0 slot 23: probe...completed console: PCI bus 0 slot 24: probe...completed console: PCI bus 0 slot 25: probe...completed console: PCI bus 0 slot 26: probe...completed console: PCI bus 0 slot 27: probe...completed console: PCI bus 0 slot 28: probe...completed console: PCI bus 0 slot 29: probe...completed console: PCI bus 0 slot 30: probe...completed console: PCI bus 0 slot 31: probe...completed console: PCIS console: PCIR console: PCIW console: PCI bus 0 slot 2/0: mem @0x40000000, reg 0x30 262144 bytes console: PCI bus 0 slot 2/0: mem @0x40040000, reg 0x20 16384 bytes console: PCI bus 0 slot 2/0: mem @0x40044000, reg 0x14 4096 bytes console: PCI bus 0 slot 1/0: mem @0x40045000, reg 0x10 256 bytes console: PCI bus 0 slot 2/0: exp @0x40000000, 262144 bytes console: PCI bus 0 slot 2/0: i/o @0x00004000, reg 0x10 32 bytes console: NETI console: RTCL console: PCID console: VGAI console: memorysize=c000000,base=8f6ff508,sysMem=8f6ef500 console: in setup_int_vect!done!VESA console: vga bios init failed, rc=-1 console: in configure console: mainbus0 (root) console: localbus0 at mainbus0 console: loopdev0 at mainbus0pcibr0 at mainbus0 console: pci0 at pcibr0 bus 0 console: ohci0 at pci0 dev 1 function 0 vendor/product: 0x106b/0x003f (serialbus, USB, interface: 0x10, revision: 0x00)usb base addr : 0xc0045000, bus_base is : 0xc0000000 console: OHCI revision: 0x00000010 console: RH: a: 0x00000203 b: 0x00000000 console: early period(0x0) console: OHCI 8c01ec00 initialized ok console: New Device 0 console: usb_get_descriptor console: bLength = 12 console: bDescriptorType =1 console: bcdUSB = 110 console: bDeviceClass =9 console: bDeviceSubClass =0 console: bDeviceProtocol =0 console: bMaxPacketSize0 =8 console: set address 1 console: usb_get_descriptor console: bLength = 12 console: bDescriptorType =1 console: bcdUSB = 110 console: bDeviceClass =9 console: bDeviceSubClass =0 console: bDeviceProtocol =0 console: bMaxPacketSize0 =8 console: idVendor =0 console: idProduct =0 console: bcdDevice =0 console: iManufacturer=0 console: iProduct =1 console: iSerialNumber=0 console: bNumConfigurations=1 console: usb_get_descriptor console: usb_get_descriptor console: get_conf_no 0 Result 25, wLength 25 console: if 0, ep 0 console: bLength=9 console: bDescriptorType=2 console: wTotalLength=19 console: bNumInterfaces=1 console: bConfigurationValue=1 console: iConfiguration=0 console: bmAttributes=40 console: MaxPower=0 console: 09 04 00 00 01 09 00 00 00 07 05 81 03 02 00 ff console: ##EP epmaxpacketin[1] = 2 console: set configuration 1 console: new device strings: Mfr=0, Product=1, SerialNumber=0 console: USB device number 1 default language ID 0x409 console: Manufacturer console: Product OHCI Root Hub console: SerialNumber console: New Device 1 console: usb_get_descriptor console: bLength = 12 console: bDescriptorType =1 console: bcdUSB = 200 console: bDeviceClass =0 console: bDeviceSubClass =0 console: bDeviceProtocol =0 console: bMaxPacketSize0 =8 console: set address 2 console: usb_get_descriptor console: bLength = 12 console: bDescriptorType =1 console: bcdUSB = 200 console: bDeviceClass =0 console: bDeviceSubClass =0 console: bDeviceProtocol =0 console: bMaxPacketSize0 =8 console: idVendor =627 console: idProduct =1 console: bcdDevice =0 console: iManufacturer=1 console: iProduct =4 console: iSerialNumber=b console: bNumConfigurations=1 console: usb_get_descriptor console: usb_get_descriptor console: get_conf_no 0 Result 34, wLength 34 console: unknown Description Type : 21 console: 09 21 11 01 00 01 22 3F 00 console: if 0, ep 0 console: bLength=9 console: bDescriptorType=2 console: wTotalLength=22 console: bNumInterfaces=1 console: bConfigurationValue=1 console: iConfiguration=8 console: bmAttributes=a0 console: MaxPower=32 console: 09 04 00 00 01 03 01 01 00 09 21 11 01 00 01 22 3f 00 07 05 81 03 08 00 0a console: ##EP epmaxpacketin[1] = 8 console: set configuration 1 console: new device strings: Mfr=1, Product=4, SerialNumber=11 console: USB device number 2 default language ID 0x409 console: Manufacturer QEMU console: Product QEMU USB Keyboard console: SerialNumber 68284-0000:00:01.0-1 console: drive at ohci0 devnum 2, Product QEMU USB Keyboard console: not configured console: New Device 2 console: usb_get_descriptor console: bLength = 12 console: bDescriptorType =1 console: bcdUSB = 200 console: bDeviceClass =0 console: bDeviceSubClass =0 console: bDeviceProtocol =0 console: bMaxPacketSize0 =8 console: set address 3 console: usb_get_descriptor console: bLength = 12 console: bDescriptorType =1 console: bcdUSB = 200 console: bDeviceClass =0 console: bDeviceSubClass =0 console: bDeviceProtocol =0 console: bMaxPacketSize0 =8 console: idVendor =627 console: idProduct =1 console: bcdDevice =0 console: iManufacturer=1 console: iProduct =3 console: iSerialNumber=a console: bNumConfigurations=1 console: usb_get_descriptor console: usb_get_descriptor console: get_conf_no 0 Result 34, wLength 34 console: unknown Description Type : 21 console: 09 21 01 00 00 01 22 4A 00 console: if 0, ep 0 console: bLength=9 console: bDescriptorType=2 console: wTotalLength=22 console: bNumInterfaces=1 console: bConfigurationValue=1 console: iConfiguration=7 console: bmAttributes=a0 console: MaxPower=32 console: 09 04 00 00 01 03 00 00 00 09 21 01 00 00 01 22 4a 00 07 05 81 03 08 00 0a console: ##EP epmaxpacketin[1] = 8 console: set configuration 1 console: new device strings: Mfr=1, Product=3, SerialNumber=10 console: USB device number 3 default language ID 0x409 console: Manufacturer QEMU console: Product QEMU USB Tablet console: SerialNumber 28754-0000:00:01.0-2 console: drive at ohci0 devnum 3, Product QEMU USB Tablet console: not configured console: drive at ohci0 devnum 1, Product OHCI Root Hub console: not configured console: vendor/product: 0x1af4/0x1000 (network, ethernet, interface: 0x00, revision: 0x00) at pci0 dev 2 function 0 not configured console: out configure console: Press <Del> to set BIOS,waiting for 3 seconds here..... console: devconfig done. console: ifinit done. console: domaininit done. console: init_proc.... console: HSTI console: SYMI console: SBDE console: [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[ console: [[ [[[[[[[[[ [[[[[ [[[[ [[[[[ [[[[[ [[[[[ [[[[[ [[[[ [[[[[ [[ console: [[ [[[[[[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[[ [[ console: [[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [ [[[ [[[ [[[[[[[[[[[[ [[[[[[[ [[[[[[ [[[ [ [[[ [[ console: [[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [[ [[ [[[ [[[ [[[[[[[ [[[[ [[[[[[ [[[ [[ [[ [[ console: [[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [[[ [ [[[ [[[[[ [[[[[[[[[[ [[[ [[[[[[ [[[ [[[ [ [[ console: [[ [[[[[[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[ [[[[ [[[[ [[[ [[[[ [[ console: [[ [[[[ [[[[[ [[[[ [[[[[ [[[[ [[[[[ [[[[[[ [[[[ [[[[[ [[ console: [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[2011 Loongson][[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[ console: Configuration [Bonito,EL,NET,SCSI,IDE] console: Version: PMON2000 3.3 (Bonito) #0: Tue Dec 22 01:58:09 UTC 2020 commit b3ece66234adbf7d4e453f0ba4f326c099ac2a76 Author: Jiaxun Yang <jiaxun.yang@flygoat.com> Date: Tue Dec 22 09:51:10 2020 +0800 . console: Supported loaders [txt, srec, elf, bin] console: Supported filesystems [net, fat, fs, disk, iso9660, socket, tty, ram] console: This software may be redistributed under the BSD copyright. console: Copyright 2000-2002, Opsycon AB, Sweden. console: Copyright 2005, ICT CAS. console: CPU GODSON3 BogoMIPS: 1327 PASS (3.89 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 4.38 s Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210112020708.62922-1-jiaxun.yang@flygoat.com> [PMD: Set timeout to 60sec, simply test for ''CPU GODSON3 BogoMIPS'] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21hw/intc/loongson_liointc: Fix per core ISR handlingJiaxun Yang1-3/+13
Per core ISR is a set of 32-bit registers spaced by 8 bytes. This patch fixed calculation of it's size and also added check of alignment at reading & writing. Fixes: Coverity CID 1438965 and CID 1438967 Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com> [PMD: Added Coverity CID] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
generated by cgit v1.1 at 2024-08-22 08:10:49 +0000