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2019-12-17ppc/pnv: Extend XiveRouter with a get_block_id() handlerCédric Le Goater4-6/+29
2019-12-17ppc/pnv: Introduce a pnv_xive_block_id() helperCédric Le Goater2-34/+33
2019-12-17ppc/xive: Synthesize interrupt from the saved IPB in the NVTCédric Le Goater1-0/+52
2019-12-17ppc/xive: Introduce a xive_tctx_ipb_update() helperCédric Le Goater2-10/+12
2019-12-17ppc/xive: Remove the get_tctx() XiveRouter handlerCédric Le Goater4-30/+0
2019-12-17ppc/xive: Move the TIMA operations to the controller modelCédric Le Goater4-33/+65
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater3-17/+40
2019-12-17spapr/xive: Configure number of servers in KVMGreg Kurz1-2/+21
2019-12-17spapr/xics: Configure number of servers in KVMGreg Kurz1-2/+19
2019-12-17spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz8-13/+28
2019-12-17linux-headers: UpdateGreg Kurz10-3/+33
2019-12-17ppc/xive: Extend the TIMA operation with a XivePresenter parameterCédric Le Goater3-31/+38
2019-12-17ppc/xive: Use the XiveFabric and XivePresenter interfacesCédric Le Goater1-31/+17
2019-12-17ppc/spapr: Implement the XiveFabric interfaceCédric Le Goater1-0/+39
2019-12-17ppc/pnv: Implement the XiveFabric interfaceCédric Le Goater1-0/+35
2019-12-17ppc/xive: Introduce a XiveFabric interfaceCédric Le Goater2-0/+32
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater3-6/+26
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater2-0/+24
2019-12-17ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater2-2/+8
2019-12-17ppc/pnv: Loop on the threads of the chip to find a matching NVTCédric Le Goater1-26/+35
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz2-19/+13
2019-12-17ppc/xive: Implement the XivePresenter interfaceCédric Le Goater3-44/+97
2019-12-17ppc/xive: Introduce a XivePresenter interfaceCédric Le Goater2-9/+49
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater3-21/+34
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater5-0/+122
2019-12-17ipmi: Add support to customize OEM functionsCédric Le Goater2-44/+48
2019-12-17ppc/xive: Check V bit in TM_PULL_POOL_CTXCédric Le Goater1-0/+5
2019-12-17ppc/xive: Introduce OS CAM line helpersCédric Le Goater1-3/+38
2019-12-17ppc/pnv: Quiesce some XIVE errorsCédric Le Goater1-1/+5
2019-12-17xive/kvm: Trigger interrupts from userspaceGreg Kurz1-14/+2
2019-12-17ppc/pnv: Remove pnv_xive_vst_size() routineCédric Le Goater1-69/+43
2019-12-17ppc/xive: Introduce helpers for the NVT idCédric Le Goater2-5/+21
2019-12-17ppc/xive: Record the IPB in the associated NVTCédric Le Goater2-2/+10
2019-12-17ppc/pnv: Add a LPC "ranges" propertyCédric Le Goater1-1/+13
2019-12-17spapr: Abort if XICS interrupt controller cannot be initializedGreg Kurz1-11/+2
2019-12-17xics: Link ICP_PROP_CPU property to ICPState::cs pointerGreg Kurz1-17/+4
2019-12-17xics: Link ICP_PROP_XICS property to ICPState::xics pointerGreg Kurz1-13/+9
2019-12-17xics: Link ICS_PROP_XICS property to ICSState::xics pointerGreg Kurz3-19/+6
2019-12-17ppc/pnv: Link "chip" property to PnvXive::chip pointerGreg Kurz2-12/+5
2019-12-17ppc/pnv: Link "chip" property to PnvCore::chip pointerGreg Kurz2-10/+4
2019-12-17ppc/pnv: Link "chip" property to PnvHomer::chip pointerGreg Kurz2-14/+14
2019-12-17ppc/pnv: Link "psi" property to PnvOCC::psi pointerGreg Kurz2-15/+13
2019-12-17ppc/pnv: Link "psi" property to PnvLpc::psi pointerGreg Kurz2-15/+12
2019-12-17xive: Link "xive" property to XiveEndSource::xrtr pointerGreg Kurz3-14/+7
2019-12-17xive: Link "xive" property to XiveSource::xive pointerGreg Kurz4-16/+8
2019-12-17xive: Link "cpu" property to XiveTCTX::cs pointerGreg Kurz1-13/+9
2019-12-17ppc/pnv: Drop "chip" link from POWER9 PSI objectGreg Kurz1-2/+0
2019-12-17ppc/pnv: Add a "/qemu" device tree nodeCédric Le Goater1-0/+3
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater5-1/+180
2019-12-16Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' ...Peter Maydell11-248/+300
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