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2021-12-22tests/qtest/virtio-net-failover: Use g_file_open_tmp() to create temporary fileThomas Huth1-3/+5
2021-12-22tests/qtest/boot-order-test: Check whether machines are availableThomas Huth1-0/+5
2021-12-22tests/qtest/cdrom-test: Check whether devices are available before using themThomas Huth1-21/+39
2021-12-22tests/qtest: Improve endianness-test to work with missing machines and devicesThomas Huth1-1/+4
2021-12-22tests/qtest: Add a function that checks whether a device is availableThomas Huth2-0/+52
2021-12-22MAINTAINERS: Update COLO Proxy sectionZhang Chen1-0/+1
2021-12-22tests/qtest: Make the filter tests independent from a specific NICThomas Huth4-40/+38
2021-12-22tests/qtest/boot-serial-test: Silence the warning about deprecated sga deviceThomas Huth1-5/+5
2021-12-22failover: Silence warning messages during qtestLaurent Vivier2-2/+9
2021-12-21Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7680/qemu into sta...Richard Henderson11-1/+3085
2021-12-21configure, meson.build: Mark support for loongarch64 hostsWANG Xuerui2-1/+6
2021-12-21linux-user: Implement CPU-specific signal handler for loongarch64 hostsWANG Xuerui1-0/+87
2021-12-21common-user: Add safe syscall handling for loongarch64 hostsWANG Xuerui1-0/+90
2021-12-21tcg/loongarch64: Register the JITWANG Xuerui1-0/+44
2021-12-21tcg/loongarch64: Implement tcg_target_initWANG Xuerui1-0/+27
2021-12-21tcg/loongarch64: Implement exit_tb/goto_tbWANG Xuerui1-0/+19
2021-12-21tcg/loongarch64: Implement tcg_target_qemu_prologueWANG Xuerui1-0/+68
2021-12-21tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st opsWANG Xuerui2-0/+355
2021-12-21tcg/loongarch64: Implement simple load/store opsWANG Xuerui2-0/+132
2021-12-21tcg/loongarch64: Implement tcg_out_callWANG Xuerui1-0/+34
2021-12-21tcg/loongarch64: Implement setcond opsWANG Xuerui2-0/+70
2021-12-21tcg/loongarch64: Implement br/brcond opsWANG Xuerui2-0/+54
2021-12-21tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu opsWANG Xuerui3-8/+74
2021-12-21tcg/loongarch64: Implement add/sub opsWANG Xuerui2-0/+40
2021-12-21tcg/loongarch64: Implement shl/shr/sar/rotl/rotr opsWANG Xuerui3-2/+94
2021-12-21tcg/loongarch64: Implement clz/ctz opsWANG Xuerui3-4/+47
2021-12-21tcg/loongarch64: Implement bswap{16,32,64} opsWANG Xuerui2-5/+37
2021-12-21tcg/loongarch64: Implement deposit/extract opsWANG Xuerui3-4/+26
2021-12-21tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc opsWANG Xuerui3-8/+98
2021-12-21tcg/loongarch64: Implement sign-/zero-extension opsWANG Xuerui3-12/+95
2021-12-21tcg/loongarch64: Implement goto_ptrWANG Xuerui2-0/+32
2021-12-21tcg/loongarch64: Implement tcg_out_mov and tcg_out_moviWANG Xuerui1-0/+137
2021-12-21tcg/loongarch64: Implement the memory barrier opWANG Xuerui1-0/+32
2021-12-21tcg/loongarch64: Implement necessary relocation operationsWANG Xuerui1-0/+66
2021-12-21tcg/loongarch64: Define the operand constraintsWANG Xuerui2-0/+80
2021-12-21tcg/loongarch64: Add register names, allocation order and input/output setsWANG Xuerui1-0/+118
2021-12-21tcg/loongarch64: Add generated instruction opcodes and encoding helpersWANG Xuerui1-0/+979
2021-12-21tcg/loongarch64: Add the tcg-target.h fileWANG Xuerui1-0/+180
2021-12-21MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainerWANG Xuerui1-0/+5
2021-12-21elf: Add machine type value for LoongArchWANG Xuerui1-0/+2
2021-12-21Merge tag 'dbus-pull-request' of https://gitlab.com/marcandre.lureau/qemu int...Richard Henderson79-401/+6249
2021-12-21MAINTAINERS: update D-Bus sectionMarc-André Lureau1-3/+7
2021-12-21ui/dbus: register D-Bus VC handlerMarc-André Lureau1-0/+53
2021-12-21ui/dbus: add chardev backend & interfaceMarc-André Lureau8-0/+476
2021-12-21option: add g_auto for QemuOptsMarc-André Lureau1-0/+2
2021-12-21chardev: make socket derivableMarc-André Lureau2-57/+85
2021-12-21chardev: teach socket to accept no addressesMarc-André Lureau1-5/+9
2021-12-21ui/dbus: add clipboard interfaceMarc-André Lureau6-0/+579
2021-12-21audio: add "dbus" audio backendMarc-André Lureau12-2/+931
2021-12-21tests: start dbus-display-testMarc-André Lureau2-0/+265
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