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2024-06-19hw/i386/pc: Remove PCMachineClass::resizable_acpi_blobPhilippe Mathieu-Daudé3-14/+0
PCMachineClass::resizable_acpi_blob was only used by the pc-i440fx-2.2 machine, which got removed. It is now always true. Remove it, simplifying acpi_build(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-18-philmd@linaro.org>
2024-06-19hw/i386/pc: Remove deprecated pc-i440fx-2.2 machinePhilippe Mathieu-Daudé5-49/+2
The pc-i440fx-2.2 machine was deprecated for the 8.2 release (see commit c7437f0ddb "docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated"), time to remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-17-philmd@linaro.org>
2024-06-19hw/mem/memory-device: Remove legacy_align from memory_device_pre_plug()Philippe Mathieu-Daudé5-13/+8
'legacy_align' is always NULL, remove it, simplifying memory_device_pre_plug(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-16-philmd@linaro.org>
2024-06-19hw/mem/pc-dimm: Remove legacy_align argument from pc_dimm_pre_plug()Philippe Mathieu-Daudé6-10/+7
'legacy_align' is always NULL, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-15-philmd@linaro.org>
2024-06-19hw/i386/pc: Remove PCMachineClass::enforce_aligned_dimmPhilippe Mathieu-Daudé3-19/+7
PCMachineClass::enforce_aligned_dimm was only used by the pc-i440fx-2.1 machine, which got removed. It is now always true. Remove it, simplifying pc_get_device_memory_range(). Update the comment in Avocado test_phybits_low_pse36(). Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-14-philmd@linaro.org>
2024-06-19hw/smbios: Remove 'smbios_uuid_encoded', simplify smbios_encode_uuid()Philippe Mathieu-Daudé1-6/+3
'smbios_encode_uuid' is always true, remove it, simplifying smbios_encode_uuid(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-13-philmd@linaro.org>
2024-06-19hw/smbios: Remove 'uuid_encoded' argument from smbios_set_defaults()Philippe Mathieu-Daudé6-11/+7
'uuid_encoded' is always true, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-12-philmd@linaro.org>
2024-06-19hw/i386/pc: Remove PCMachineClass::smbios_uuid_encodedPhilippe Mathieu-Daudé3-4/+1
PCMachineClass::smbios_uuid_encoded was only used by the pc-i440fx-2.1 machine, which got removed. It is now always true, remove it. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-11-philmd@linaro.org>
2024-06-19target/i386/kvm: Remove x86_cpu_change_kvm_default() and 'kvm-cpu.h'Philippe Mathieu-Daudé2-43/+1
x86_cpu_change_kvm_default() was only used out of kvm-cpu.c by the pc-i440fx-2.1 machine, which got removed. Make it static, and remove its declaration. "kvm-cpu.h" is now empty, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-10-philmd@linaro.org>
2024-06-19hw/i386/pc: Remove deprecated pc-i440fx-2.1 machinePhilippe Mathieu-Daudé5-35/+2
The pc-i440fx-2.1 machine was deprecated for the 8.2 release (see commit c7437f0ddb "docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated"), time to remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-9-philmd@linaro.org>
2024-06-19hw/acpi/ich9: Remove dead code related to 'acpi_memory_hotplug'Philippe Mathieu-Daudé1-22/+6
acpi_memory_hotplug::is_enabled is set to %true once via ich9_lpc_initfn() -> ich9_pm_add_properties(). No need to check it, so remove now dead code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-8-philmd@linaro.org>
2024-06-19hw/acpi/ich9: Remove 'memory-hotplug-support' propertyPhilippe Mathieu-Daudé1-18/+0
No external code sets the 'memory-hotplug-support' property, remove it. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-7-philmd@linaro.org>
2024-06-19hw/i386/acpi: Remove PCMachineClass::legacy_acpi_table_sizePhilippe Mathieu-Daudé2-53/+13
PCMachineClass::legacy_acpi_table_size was only used by the pc-i440fx-2.0 machine, which got removed. Remove it and simplify acpi_build(). Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240617071118.60464-6-philmd@linaro.org>
2024-06-19hw/usb/hcd-xhci: Remove XHCI_FLAG_SS_FIRST flagPhilippe Mathieu-Daudé4-39/+9
XHCI_FLAG_SS_FIRST was only used by the pc-i440fx-2.0 machine, which got removed. Remove it and simplify various functions in hcd-xhci.c. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-5-philmd@linaro.org>
2024-06-19hw/usb/hcd-xhci: Remove XHCI_FLAG_FORCE_PCIE_ENDCAP flagPhilippe Mathieu-Daudé3-5/+1
XHCI_FLAG_FORCE_PCIE_ENDCAP was only used by the pc-i440fx-2.0 machine, which got removed. Remove it and simplify usb_xhci_pci_realize(). Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-4-philmd@linaro.org>
2024-06-19hw/i386/pc: Remove deprecated pc-i440fx-2.0 machinePhilippe Mathieu-Daudé5-57/+2
The pc-i440fx-2.0 machine was deprecated for the 8.2 release (see commit c7437f0ddb "docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated"), time to remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-3-philmd@linaro.org>
2024-06-19hw/i386/pc: Deprecate 2.4 to 2.12 pc-i440fx machinesPhilippe Mathieu-Daudé2-3/+3
Similarly to the commit c7437f0ddb "docs/about: Mark the old pc-i440fx-2.0 - 2.3 machine types as deprecated", deprecate the 2.4 to 2.12 machines. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-2-philmd@linaro.org>
2024-06-18Merge tag 'edgar/xilinx-queue-2024-06-17.for-upstream' of ↵Richard Henderson3-5/+33
https://gitlab.com/edgar.iglesias/qemu into staging Xilinx queue: hw/dma: Add error handling for loading descriptions failing (Fea Wang) # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEErET+3BT38evtv0FRKcWWeA9ryoMFAmZxg3oACgkQKcWWeA9r # yoPMTAf/VwI/fJ/bK0LgDSaZbh+D+IowM1d/FyLslMSIsbXk+gEmVeQIOG448myl # mpbm1ijlQieSHBeJhDb/Pa2HmUI6t60wtSPaQtTlOziu/2lXkp2WXb3Y7U9QIQpJ # OrG6n0xrQse5tNYE4C+X4nvYXbCM0ij/W5+XV3yVTTc4qiLN73keJ1Idd7wONGqY # igaYbsiT82FH61qUuYNm1t+vagSEj3jSFBe6BOdRCbkP9NSuqJg5HVkprUqRgGAW # sG2ig99pHInNAlMKwNCLPU3nZcaeN+jy8DwGvsUFymu/wxEl7ZoBj9iv8aQUm+Tj # 0Tl3XUTqzb+HAK66MkquYA83BIMfjQ== # =bbD0 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 18 Jun 2024 05:54:18 AM PDT # gpg: using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown] # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [full] * tag 'edgar/xilinx-queue-2024-06-17.for-upstream' of https://gitlab.com/edgar.iglesias/qemu: hw/net: Fix the transmission return size hw/dma: Add a trace log for a description loading failure hw/dma: Enhance error handling in loading description Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-18hw/net: Fix the transmission return sizeFea.Wang1-1/+1
Fix the transmission return size because not all bytes could be transmitted successfully. So, return a successful length instead of a constant value. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-06-18hw/dma: Add a trace log for a description loading failureFea.Wang2-0/+6
Due to a description loading failure, adding a trace log makes observing the DMA behavior easy. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-06-17hw/dma: Enhance error handling in loading descriptionFea.Wang1-4/+26
Loading a description from memory may cause a bus-error. In this case, the DMA should stop working, set the error flag, and return the failure value. When calling the loading a description function, it should be noticed that the function may return a failure value. Breaking the loop in this case is one of the possible ways to handle it. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
2024-06-17Merge tag 'dirtylimit-dirtyrate-pull-request-20240617' of ↵Richard Henderson1-1/+1
https://github.com/newfriday/qemu into staging dirtylimit-dirtyrate-pull-request-20240617: Fix a segmentation fault # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaF0CINwmSCgVLlfC3/Ij1rP+y5wFAmZwVvkACgkQ3/Ij1rP+ # y5xAyQ//T0ABDLvAmtkUWRlRxZvQBDiZdFuWiPv3ntA5GdL04hL9Mlxof0rmMBrM # VCFLYOzDImy/cf9SawieUIUyKmhY0TN66PEupoJBMm/k+bccOQi/7uuCscau4YjA # I5f1Ms7GI8tSMyigoPSKmkPO5gvTwptkM3AOtuKs0w/8sFt/FuBWCYi81Xye7eQe # X5idndqaLbylg0PacoSPARL1xeXUaokpbvpbg3HAIVH1zDNiNSBkVZnysURb/OT1 # wjkY5OtD9s5MCdnqPImkoCn2WXsITtL+5YlGUz3+xUQlG+pHIaJIy4rK+y3v6RgX # jgvLCLudeVSV//DLYnitp9wrJcpqoINijdvuSSTFyjANN3SsGN9A90TTZSaV5oyg # TMLBpiGqAWGDnXvRCq3vg3tb8gVhBrpISF0AF+6UvuiyIVIfMJPSvSekEXKfxNs8 # JoqzM1yEjgzr+d6X5+jN0kRm61kcmMP09JOKBHFwx3ZlCuYVr3XeR8YVClMJVqFw # ZC0WaTSs69ldeU2pHn6d451aMgip+l7ZdDcROCJEGmQxZSc7JXNxcJ9RMRINutTp # ljw86yTs+tLqrtg6FZ+eSBPJCqHFN6hdn9sXlIgJFV+bIj5dO4M6FeNwWvDo6ZaK # JwjBlX6FOIwUtGpXaRy+YSECtiEagRsIrFIcrwgYJAL52c59LAc= # =wVGj # -----END PGP SIGNATURE----- # gpg: Signature made Mon 17 Jun 2024 08:32:09 AM PDT # gpg: using RSA key 685D0220DC264828152E57C2DFF223D6B3FECB9C # gpg: Good signature from "Yong Huang <yong.huang@smartx.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 685D 0220 DC26 4828 152E 57C2 DFF2 23D6 B3FE CB9C * tag 'dirtylimit-dirtyrate-pull-request-20240617' of https://github.com/newfriday/qemu: migration/dirtyrate: Fix segmentation fault Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-17Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson12-1219/+1173
* i386: fix issue with cache topology passthrough * scsi-disk: migrate emulated requests * i386/sev: fix Coverity issues * i386/tcg: more conversions to new decoder # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmZv6kMUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOn4Af/evnpsae1fm8may1NQmmezKiks/4X # cR0GaQ7w75Oas05jKsG7Xnrq3Vn6p5wllf3Wf00p7F1iJX18azY9rQgIsUVUgVem # /EIZk1eM6+mDxuIG0taPxc5Aw3cfIBWAjUmzsXrSr55e/wyiIxZCeUo2zk8Il+iL # Z4ceNzY5PZzc2Fl10D3cGs/+ynfiDM53ucwe3ve2T6NrxEVfKQPp5jkIUkBUba6z # zM5O4Q5KTEZYVth1gbDTB/uUJLUFjQ12kCQfRCNX+bEPDHwARr0UWr/Oxtz0jZSd # FvXohz7tI+v+ph0xHyE4tEFqryvLCII1td2ohTAYZZXNGkjK6XZildngBw== # =m4BE # -----END PGP SIGNATURE----- # gpg: Signature made Mon 17 Jun 2024 12:48:19 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (25 commits) target/i386: SEV: do not assume machine->cgs is SEV target/i386: convert CMPXCHG to new decoder target/i386: convert XADD to new decoder target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT to new decoder target/i386: convert SHLD/SHRD to new decoder target/i386: adapt gen_shift_count for SHLD/SHRD target/i386: pull load/writeback out of gen_shiftd_rm_T1 target/i386: convert non-grouped, helper-based 2-byte opcodes target/i386: split X86_CHECK_prot into PE and VM86 checks target/i386: finish converting 0F AE to the new decoder target/i386: fix bad sorting of entries in the 0F table target/i386: replace read_crN helper with read_cr8 target/i386: convert MOV from/to CR and DR to new decoder target/i386: fix processing of intercept 0 (read CR0) target/i386: replace NoSeg special with NoLoadEA target/i386: change X86_ENTRYwr to use T0, use it for moves target/i386: change X86_ENTRYr to use T0 target/i386: put BLS* input in T1, use generic flag writeback target/i386: rewrite flags writeback for ADCX/ADOX target/i386: remove CPUX86State argument from generator functions ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-17Merge tag 'pull-aspeed-20240617' of https://github.com/legoater/qemu into ↵Richard Henderson24-58/+2351
staging aspeed queue: * Add AST2700 support # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmZvtLUACgkQUaNDx8/7 # 7KH8Ew/+K7OJYUsRhuLByLjaQ8kCsVdxMCFLtpCL9t6AgrMUXaI6WkkynPMKITQQ # AHocO76TsWRMp962obnjvXgVRCrtvOI2W5jvgp1Gr554tW7YQClLiGhuf1FeORS9 # ZQhWryoC8vK8ymC7dAS5cyuiddWFUGC04P9lb9oXr88n6goZ1xRfKwM+RttgfCAm # 79SsK7g3TS8QOWH1kQwIQZyJKzwrw7bTM3Ijv9NmVKa050zWquMRZQeY18fgO6Ae # p/pGpkf4Bc5iv+kIXoI4UN7Cx74aZoKInQ+DA71gtCWh/s09j9PkvOAfKWYAozD+ # VSaLvw4rvhRxgbs1SjoiMb5dDjJhngfzLhJX/P2FD1LCHRk+/uxk3fDDp2AqvQ6z # IuWPb8FgWHqeiigcXkTW1JgUS85quIbjWBxreIrQiq+zR50EQy49elMRhzJlKsqZ # 3/ulk7xf+5M1+wS4bo7r8LPk5K8mFw9b4cxfnx0feZCjrl4ZfeWyDtaKzCAU0MJq # KfpHo9R98imjVmcRWUouTaFow33OXheLdPFO8PofVnT38a4KIWlkin3zFMdTOAk+ # f8kWMPlXlRpKBYsjvP2aCpoY6CY8bHskdBH7xysM2W1FfKTw3dwZRpt4dgVPxqYj # KZXiKxzwnC2gGi/wn+EdhZwYy1nNSZYGK8s+jxBXi2UBrwv4PpA= # =TnR8 # -----END PGP SIGNATURE----- # gpg: Signature made Sun 16 Jun 2024 08:59:49 PM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240617' of https://github.com/legoater/qemu: MAINTAINERS: Add reviewers for ASPEED BMCs docs:aspeed: Add AST2700 Evaluation board test/avocado/machine_aspeed.py: Add AST2700 test case aspeed/soc: fix incorrect dram size for AST2700 aspeed: Add an AST2700 eval board aspeed/soc: Add AST2700 support aspeed/intc: Add AST2700 support aspeed/scu: Add AST2700 support aspeed/smc: Add AST2700 support aspeed/smc: support different memory region ops for SMC flash region aspeed/smc: support 64 bits dma dram address aspeed/smc: support dma start length and 1 byte length unit aspeed/smc: correct device description aspeed/sdmc: Add AST2700 support aspeed/sdmc: fix coding style aspeed/sdmc: remove redundant macros aspeed/sli: Add AST2700 support aspeed/wdt: Add AST2700 support aspeed/smc: Reintroduce "dram-base" property for AST2700 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-17migration/dirtyrate: Fix segmentation faultMasato Imai1-1/+1
Since the kvm_dirty_ring_enabled function accesses a null kvm_state pointer when the KVM acceleration parameter is not specified, running calc_dirty_rate with the -r or -b option causes a segmentation fault. Signed-off-by: Masato Imai <mii@sfc.wide.ad.jp> Message-ID: <20240507025010.1968881-1-mii@sfc.wide.ad.jp> [Assert kvm_state when kvm_dirty_ring_enabled was called to fix it. - Hyman] Signed-off-by: Hyman Huang <yong.huang@smartx.com>
2024-06-17target/i386: SEV: do not assume machine->cgs is SEVPaolo Bonzini1-1/+3
There can be other confidential computing classes that are not derived from sev-common. Avoid aborting when encountering them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: convert CMPXCHG to new decoderPaolo Bonzini3-80/+53
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: convert XADD to new decoderPaolo Bonzini3-36/+26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: convert LZCNT/TZCNT/BSF/BSR/POPCNT to new decoderPaolo Bonzini4-76/+133
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: convert SHLD/SHRD to new decoderPaolo Bonzini3-84/+50
Use the same flag generation code as SHL and SHR, but use the existing gen_shiftd_rm_T1 function to compute the result as well as CC_SRC. Decoding-wise, SHLD/SHRD by immediate count as a 4 operand instruction because s->T0 and s->T1 actually occupy three op slots. The infrastructure used by opcodes in the 0F 3A table works fine. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: adapt gen_shift_count for SHLD/SHRDPaolo Bonzini1-10/+10
SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either 1 or CL - and therefore decode->op[2] is taken by the low part of the register being shifted. Pass X86_OP_* to gen_shift_count from its current callers and hardcode cpu_regs[R_ECX] as the shift count. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: pull load/writeback out of gen_shiftd_rm_T1Paolo Bonzini1-41/+14
Use gen_ld_modrm/gen_st_modrm, moving them and gen_shift_flags to the caller. This way, gen_shiftd_rm_T1 becomes something that the new decoder can call. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: convert non-grouped, helper-based 2-byte opcodesPaolo Bonzini5-170/+206
These have very simple generators and no need for complex group decoding. Apart from LAR/LSL which are simplified to use gen_op_deposit_reg_v and movcond, the code is generally lifted from translate.c into the generators. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: split X86_CHECK_prot into PE and VM86 checksPaolo Bonzini2-4/+13
SYSENTER is allowed in VM86 mode, but not in real mode. Split the check so that PE and !VM86 are covered by separate bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: finish converting 0F AE to the new decoderPaolo Bonzini4-194/+129
This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish the job. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: fix bad sorting of entries in the 0F tablePaolo Bonzini1-47/+46
Aesthetic change only. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: replace read_crN helper with read_cr8Paolo Bonzini3-17/+7
All other control registers are stored plainly in CPUX86State. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-17target/i386: convert MOV from/to CR and DR to new decoderPaolo Bonzini4-84/+81
Complete implementation of C and D operand types, then the operations are just MOVs. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-06-16MAINTAINERS: Add reviewers for ASPEED BMCsJamin Lin1-0/+3
Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin" to be reviewers of ASPEED BMCs. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-06-16docs:aspeed: Add AST2700 Evaluation boardJamin Lin1-4/+35
Add AST2700 Evaluation board and its boot command. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-06-16test/avocado/machine_aspeed.py: Add AST2700 test caseJamin Lin1-0/+62
Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board. It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os images to dram first which base address is 0x400000000. Then, boot and launch 4 cpu cores. ``` qemu-system-aarch64 -machine ast2700-evb -device loader,force-raw=on,addr=0x400000000,file=workdir/u-boot-nodtb.bin \ -device loader,force-raw=on,addr=uboot_dtb_load_addr,file=workdir/u-boot.dtb\ -device loader,force-raw=on,addr=0x430000000,file=workdir/bl31.bin\ -device loader,force-raw=on,addr=0x430080000,file=workdir/optee/tee-raw.bin\ -device loader,cpu-num=0,addr=0x430000000 \ -device loader,cpu-num=1,addr=0x430000000 \ -device loader,cpu-num=2,addr=0x430000000 \ -device loader,cpu-num=3,addr=0x430000000 \ -smp 4 \ -drive file=workdir/image-bmc,format=raw,if=mtd ``` A test image is downloaded from the ASPEED Forked OpenBMC GitHub release repository : https://github.com/AspeedTech-BMC/openbmc/releases/ Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-06-16aspeed/soc: fix incorrect dram size for AST2700Jamin Lin2-1/+88
AST2700 dram size calculation is not back compatible AST2600. According to the DDR capacity hardware behavior, if users write the data to the address which is beyond the ram size, it would write the data to the "address % ram_size". For example: a. sdram base address "0x4 00000000" b. sdram size 1 GiB The available address range is from "0x4 00000000" to "0x4 3FFFFFFF". If users write 0x12345678 to address "0x5 00000000", the value of DRAM address 0 (base address 0x4 00000000) will be 0x12345678. Add aspeed_soc_ast2700_dram_init to calculate the dram size and add memory I/O whose address range is from "max_ram_size - ram_size" to max_ram_size and its read/write handler to emulate DDR capacity hardware behavior. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed: Add an AST2700 eval boardJamin Lin1-0/+32
AST2700 CPU is ARM Cortex-A35 which is 64 bits. Add TARGET_AARCH64 to build this machine. According to the design of ast2700, it has a bootmcu(riscv-32) which is used for executing SPL. Then, CPUs(cortex-a35) execute u-boot, kernel and rofs. Currently, qemu not support emulate two CPU architectures at the same machine. Therefore, qemu will only support to emulate CPU(cortex-a35) side for ast2700 Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-06-16aspeed/soc: Add AST2700 supportJamin Lin3-2/+590
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU). AST2700 SOC and its interrupt controller are too complex to handle in the common Aspeed SoC framework. We introduce a new ast2700 class with instance_init and realize handlers. AST2700 is a 64 bits quad core cpus and support 8 watchdog. Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8. In addition, update AspeedSocState to support scuio, sli, sliio and intc. Add TYPE_ASPEED27X0_SOC machine type. The SDMC controller is unlocked at SPL stage. At present, only supports to emulate booting start from u-boot stage. Set SDMC controller unlocked by default. In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts. It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136. And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to GICINT or-gates instead of GIC device. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/intc: Add AST2700 supportJamin Lin4-0/+419
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of INT 128 to INT136 combines 32 interrupts. Introduce a new aspeed_intc class with instance_init and realize handlers. So far, this model only supports GICINT128 to GICINT136. It creates 9 GICINT or-gates to connect 32 interrupts sources from GICINT128 to GICINT136 as IRQ GPIO-OUTPUT pins. Then, this model registers IRQ handler with its IRQ GPIO-INPUT pins which connect to GICINT or-gates. And creates 9 GICINT IRQ GPIO-OUTPUT pins which connect to GIC device with GIC IRQ 128 to 136. If one interrupt source from GICINT128 to GICINT136 set irq, the OR-GATE irq callback function is called and set irq to INTC by OR-GATE GPIO-OUTPUT pins. Then, the INTC irq callback function is called and set irq to GIC by its GICINT IRQ GPIO-OUTPUT pins. Finally, the GIC irq callback function is called and set irq to CPUs and CPUs execute Interrupt Service Routine (ISR). Block diagram of GICINT132: GICINT132 ETH1 +-----------+ +-------->+0 3| ETH2 | 4| +-------->+1 5| ETH3 | 6| +-------->+2 19| INTC GIC UART0 | 20| +--------------------------+ +-------->+7 21| | | +--------------+ UART1 | 22| |orgate0 +----> output_pin0+----------->+GIC128 | +-------->+8 23| | | | | UART2 | 24| |orgate1 +----> output_pin1+----------->+GIC129 | +-------->+9 25| | | | | UART3 | 26| |orgate2 +----> output_pin2+----------->+GIC130 | +--------->10 27| | | | | UART5 | 28| |orgate3 +----> output_pin3+----------->+GIC131 | +-------->+11 29| | | | | UART6 | +----------->+orgate4 +----> output_pin4+----------->+GIC132 | +-------->+12 30| | | | | UART7 | 31| |orgate5 +----> output_pin5+----------->+GIC133 | +-------->+13 | | | | | UART8 | OR[0:31] | |orgate6 +----> output_pin6+----------->+GIC134 | ---------->14 | | | | | UART9 | | |orgate7 +----> output_pin7+----------->+GIC135 | --------->+15 | | | | | UART10 | | |orgate8 +----> output_pin8+----------->+GIC136 | --------->+16 | | | +--------------+ UART11 | | +--------------------------+ +-------->+17 | UART12 | | +--------->18 | | | | | | | +-----------+ Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> [clg: Fixed class_size in TYPE_ASPEED_INTC definition ]
2024-06-16aspeed/scu: Add AST2700 supportJamin Lin3-6/+351
AST2700 have two SCU controllers which are SCU and SCUIO. Both SCU and SCUIO registers are not compatible previous SOCs , introduces new registers and adds ast2700 scu, sucio class init handler. The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and the pclk divider selection of SCU is defined in SCU280[25:23]. Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function and trace-event for AST2700 SCU and SCUIO. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [clg: Fixed spelling : Unhandeled -> Unhandled ]
2024-06-16aspeed/smc: Add AST2700 supportJamin Lin1-1/+233
AST2700 fmc/spi controller's address decoding unit is 64KB and only bits [31:16] are used for decoding. Introduce seg_to_reg and reg_to_seg handlers for ast2700 fmc/spi controller. In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler. AST2700 is a 64 bits quad core CPUs(Cortex-a35). Introduce a new "aspeed_2700_smc_flash_ops" and set its valid "max_access_size" 8 for 64 bits data format access. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: support different memory region ops for SMC flash regionJamin Lin2-1/+14
It set "aspeed_smc_flash_ops" struct which containing read and write callbacks to be used when I/O is performed on the SMC flash region. And it set the valid max_access_size 4 by default for all ASPEED SMC models. However, the valid max_access_size 4 only support 32 bits CPUs. To support all ASPEED SMC model, introduce a new "const MemoryRegionOps *" attribute in AspeedSMCClass and use it in aspeed_smc_flash_realize function. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: support 64 bits dma dram addressJamin Lin2-9/+44
AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM Side Address High Part(0x7C)" register to support 64 bits dma dram address. Add helper routines functions to compute the dma dram address, new features and update trace-event to support 64 bits dram address. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed/smc: support dma start length and 1 byte length unitJamin Lin2-8/+36
DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA length is from 4 bytes to 32MB for AST2500. In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte data for AST2600 and AST10x0 and 4 bytes data for AST2500. To support all ASPEED SOCs, adds dma_start_length parameter to store the start length, add helper routines function to compute the dma length and update DMA_LENGTH mask to "1FFFFFF" to support dma 1 byte length unit for AST2600 and AST1030. Currently, only supports dma length 4 bytes aligned. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
generated by cgit v1.1 at 2024-09-27 10:07:29 +0000