| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-05-25 | target/arm: Implement SVE2 MATCH, NMATCH | Stephen Long | 4 | -0/+101 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise ternary operations | Richard Henderson | 4 | -0/+281 |
| 2021-05-25 | target/arm: Implement SVE2 WHILERW, WHILEWR | Richard Henderson | 2 | -0/+70 |
| 2021-05-25 | target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS | Richard Henderson | 4 | -17/+82 |
| 2021-05-25 | target/arm: Implement SVE2 SQSHRN, SQRSHRN | Richard Henderson | 4 | -0/+149 |
| 2021-05-25 | target/arm: Implement SVE2 UQSHRN, UQRSHRN | Richard Henderson | 4 | -0/+137 |
| 2021-05-25 | target/arm: Implement SVE2 SQSHRUN, SQRSHRUN | Richard Henderson | 4 | -0/+153 |
| 2021-05-25 | target/arm: Implement SVE2 SHRN, RSHRN | Richard Henderson | 4 | -2/+236 |
| 2021-05-25 | target/arm: Implement SVE2 floating-point pairwise | Stephen Long | 4 | -0/+114 |
| 2021-05-25 | target/arm: Implement SVE2 saturating extract narrow | Richard Henderson | 4 | -0/+330 |
| 2021-05-25 | target/arm: Implement SVE2 integer absolute difference and accumulate | Richard Henderson | 2 | -0/+27 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift and insert | Richard Henderson | 2 | -0/+15 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift right and accumulate | Richard Henderson | 2 | -0/+42 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract long with carry | Richard Henderson | 4 | -0/+66 |
| 2021-05-25 | target/arm: Implement SVE2 integer absolute difference and accumulate long | Richard Henderson | 4 | -0/+104 |
| 2021-05-25 | target/arm: Implement SVE2 complex integer add | Richard Henderson | 4 | -0/+92 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise permute | Richard Henderson | 5 | -0/+135 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise exclusive-or interleaved | Richard Henderson | 4 | -0/+49 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift left long | Richard Henderson | 4 | -0/+197 |
| 2021-05-25 | target/arm: Implement SVE2 PMULLB, PMULLT | Richard Henderson | 5 | -0/+59 |
| 2021-05-25 | target/arm: Implement SVE2 integer multiply long | Richard Henderson | 4 | -0/+64 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract wide | Richard Henderson | 4 | -0/+78 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract interleaved long | Richard Henderson | 2 | -0/+10 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract long | Richard Henderson | 4 | -0/+132 |
| 2021-05-25 | target/arm: Implement SVE2 saturating add/subtract (predicated) | Richard Henderson | 4 | -56/+210 |
| 2021-05-25 | target/arm: Implement SVE2 integer pairwise arithmetic | Richard Henderson | 4 | -0/+135 |
| 2021-05-25 | target/arm: Implement SVE2 integer halving add/subtract (predicated) | Richard Henderson | 4 | -0/+112 |
| 2021-05-25 | target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) | Richard Henderson | 4 | -0/+176 |
| 2021-05-25 | target/arm: Split out saturating/rounding shifts from neon | Richard Henderson | 2 | -430/+227 |
| 2021-05-25 | target/arm: Implement SVE2 integer unary operations (predicated) | Richard Henderson | 4 | -0/+88 |
| 2021-05-25 | target/arm: Implement SVE2 integer pairwise add and accumulate long | Richard Henderson | 4 | -0/+102 |
| 2021-05-25 | target/arm: Implement SVE2 Integer Multiply - Unpredicated | Richard Henderson | 4 | -0/+166 |
| 2021-05-25 | target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 | Richard Henderson | 3 | -8/+32 |
| 2021-05-25 | disas/libvixl: Protect C system header for C++ compiler | Philippe Mathieu-Daudé | 6 | -11/+15 |
| 2021-05-25 | target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type | Rebecca Cran | 1 | -0/+1 |
| 2021-05-25 | target/arm: Add support for FEAT_TLBIOS | Rebecca Cran | 2 | -0/+48 |
| 2021-05-25 | target/arm: Add support for FEAT_TLBIRANGE | Rebecca Cran | 2 | -0/+286 |
| 2021-05-25 | accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1] | Richard Henderson | 1 | -6/+6 |
| 2021-05-25 | accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0 | Richard Henderson | 1 | -6/+5 |
| 2021-05-25 | accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced() | Richard Henderson | 2 | -7/+32 |
| 2021-05-25 | accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus() | Richard Henderson | 2 | -7/+30 |
| 2021-05-25 | accel/tcg: Add tlb_flush_range_by_mmuidx() | Richard Henderson | 2 | -5/+34 |
| 2021-05-25 | accel/tcg: Remove {encode,decode}_pbm_to_runon | Richard Henderson | 1 | -66/+20 |
| 2021-05-25 | accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData | Richard Henderson | 1 | -12/+12 |
| 2021-05-25 | accel/tcg: Pass length argument to tlb_flush_range_locked() | Richard Henderson | 1 | -15/+33 |
| 2021-05-25 | accel/tcg: Replace g_new() + memcpy() by g_memdup() | Richard Henderson | 1 | -11/+4 |
| 2021-05-25 | target/arm: Use correct SP in M-profile exception return | Peter Maydell | 1 | -1/+2 |
| 2021-05-25 | hw/arm: Model TCMs in the SSE-300, not the AN547 | Peter Maydell | 3 | -12/+21 |
| 2021-05-25 | hw/arm/mps2-tz: Allow board to specify a boot RAM size | Peter Maydell | 1 | -0/+13 |
| 2021-05-25 | hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD | Peter Maydell | 1 | -4/+4 |
