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2021-10-08macfb: add common monitor modes supported by the MacOS toolbox ROMMark Cave-Ayland4-21/+156
2021-10-08macfb: add qdev property to specify display typeMark Cave-Ayland3-1/+12
2021-10-08macfb: implement mode sense to allow display type to be detectedMark Cave-Ayland3-2/+137
2021-10-08macfb: add trace events for reading and writing the control registersMark Cave-Ayland2-1/+11
2021-10-08macfb: use memory_region_init_ram() in macfb_common_realize() for the framebu...Mark Cave-Ayland1-3/+2
2021-10-08macfb: fix overflow of color_palette arrayMark Cave-Ayland1-1/+3
2021-10-08macfb: fix invalid object reference in macfb_common_realize()Mark Cave-Ayland1-1/+1
2021-10-08macfb: update macfb.c to use the Error API best practicesMark Cave-Ayland1-8/+8
2021-10-08macfb: handle errors that occur during realizeMark Cave-Ayland1-0/+11
2021-10-07Merge remote-tracking branch 'remotes/vsementsov/tags/pull-jobs-2021-10-07-v2...Richard Henderson12-92/+316
2021-10-07Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson15-479/+516
2021-10-07iotests: Add mirror-ready-cancel-error testHanna Reitz2-0/+148
2021-10-07mirror: Do not clear .cancelledHanna Reitz2-3/+3
2021-10-07mirror: Stop active mirroring after force-cancelHanna Reitz1-0/+2
2021-10-07mirror: Check job_is_cancelled() earlierHanna Reitz1-5/+5
2021-10-07mirror: Use job_is_cancelled()Hanna Reitz1-1/+1
2021-10-07job: Add job_cancel_requested()Hanna Reitz3-9/+23
2021-10-07job: Do not soft-cancel after a job is doneHanna Reitz1-4/+21
2021-10-07jobs: Give Job.force_cancel more meaningHanna Reitz4-9/+35
2021-10-07job: @force parameter for job_cancel_sync()Hanna Reitz7-50/+50
2021-10-07job: Force-cancel jobs in a failed transactionHanna Reitz1-1/+6
2021-10-07mirror: Drop s->syncedHanna Reitz1-10/+9
2021-10-07mirror: Keep s->synced on errorHanna Reitz1-1/+0
2021-10-07job: Context changes in job_completed_txn_abort()Hanna Reitz1-5/+17
2021-10-07hw/riscv: shakti_c: Mark as not user creatableAlistair Francis1-0/+7
2021-10-07hw/dma: sifive_pdma: Don't run DMA when channel is disclaimedBin Meng1-2/+9
2021-10-07hw/dma: sifive_pdma: Fix Control.claim bit detectionBin Meng1-1/+1
2021-10-07hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUARTPhilippe Mathieu-Daudé2-16/+93
2021-10-07hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion containerPhilippe Mathieu-Daudé2-3/+9
2021-10-07hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definitionPhilippe Mathieu-Daudé2-8/+10
2021-10-07hw/char: sifive_uart: Register device in 'input' categoryBin Meng1-0/+1
2021-10-07hw/char: shakti_uart: Register device in 'input' categoryBin Meng1-0/+1
2021-10-07hw/char: ibex_uart: Register device in 'input' categoryBin Meng1-0/+1
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2-13/+21
2021-10-07disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich1-3/+154
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich3-33/+0
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2-77/+21
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich4-79/+15
2021-10-07target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich1-0/+6
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich4-55/+18
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2-41/+50
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich4-1/+65
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2-18/+24
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2-78/+0
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2-63/+0
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2-13/+23
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2-0/+8
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich1-3/+5
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich1-1/+1
2021-10-07target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich1-2/+4