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2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li3-6/+20
Add support for the zmmul extension v0.1. This extension includes all multiplication operations from the M extension but not the divide ops. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220531030732.3850-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader sectionAlistair Francis1-0/+1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220509091339.26016-1-alistair.francis@wdc.com>
2022-06-09Merge tag 'pull-xen-20220609' of ↵Richard Henderson4-48/+48
https://xenbits.xen.org/git-http/people/aperard/qemu-dm into staging Xen patches - PIIX3-IDE Xen cleanup # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEE+AwAYwjiLP2KkueYDPVXL9f7Va8FAmKh/A8ACgkQDPVXL9f7 # Va80HAf/RfBfHiHQnZOiixu+drHNcyxHDqeEcd5OqWJssD/uwd/s+DfjUm7q4t3p # AOOf3kczj+S7LomVi4CU0qW6/edY6Jyq37aIQnCwwG35/U297gyqQGaLftDRspWO # quBGd/66+3wSttRDY9zuTvAWRX1IBk+7ON67TXQxnNyeE+JsstzkZw86939BO1L/ # Rp1LwwtNPS8rnT1YMSWBaFGjRbxOBzF/cRVLxwv+XBYJw/DGKVeB41I5MnNT+ZlP # MC2PVr2wZM6ki9xYdivn8d4IKECgeXclK3YSOKlYNbWW8bVvFde9j/DMty7k2geE # 8JMsdIGTvVbb9zwe85SaguWRWlArpA== # =cyLu # -----END PGP SIGNATURE----- # gpg: Signature made Thu 09 Jun 2022 06:56:31 AM PDT # gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF # gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [unknown] # gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8 # Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF * tag 'pull-xen-20220609' of https://xenbits.xen.org/git-http/people/aperard/qemu-dm: include/hw/ide: Unexport pci_piix3_xen_ide_unplug() hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug() hw/ide/piix: Remove redundant "piix3-ide-xen" device class Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-09include/hw/ide: Unexport pci_piix3_xen_ide_unplug()Bernhard Beschow3-50/+47
This function was declared in a generic and public header, implemented in a device-specific source file but only used in xen_platform. Given its 'aux' parameter, this function is more xen-specific than piix-specific. Also, the hardcoded magic constants seem to be generic and related to PCIIDEState and IDEBus rather than piix. Therefore, move this function to xen_platform, unexport it, and drop the "piix3" in the function name as well. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Paul Durrant <paul@xen.org> Acked-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220513180957.90514-4-shentey@gmail.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-06-09hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug()Bernhard Beschow1-0/+11
The comment is based on commit message ae4d2eb273b167dad748ea4249720319240b1ac2 'xen-platform: add missing disk unplug option'. Since it seems to describe design decisions and limitations that still apply it seems worth having. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20220513180957.90514-3-shentey@gmail.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-06-09hw/ide/piix: Remove redundant "piix3-ide-xen" device classBernhard Beschow2-9/+1
Commit 0f8445820f11a69154309863960328dda3dc1ad4 'xen: piix reuse pci generic class init function' already resolved redundant code which in turn rendered piix3-ide-xen redundant. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Message-Id: <20220513180957.90514-2-shentey@gmail.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
2022-06-09Merge tag 'pull-target-arm-20220609' of ↵Richard Henderson50-3036/+3239
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/arm: Declare support for FEAT_RASv1p1 * target/arm: Implement FEAT_DoubleFault * Fix 'writeable' typos * xlnx_dp: Implement vblank interrupt * target/arm: Move page-table-walk code to ptw.c * target/arm: Preparatory patches for SME support # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmKht40ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3p/hEACkUlUhKStyMCimLZJQ2wfG # rBO6zHPNVDWtWqUy/1e5HgeU6HXqk0TXLGIbk+6/2y1wos2KGHPOIjIw0miPuZF9 # tsVvwjKlnOPecJc5tm3vxPswBK29Rp7BtNTIXSlGOcByOK1L94ern5pi29QK1ltm # rZ8vbzJTJ58vCTUkYjcnIeLWAWzgiEgVdEWwl7+3dGIr0x9uawfku/eFd0zFb5+v # TtBUz0d92te7SehtiGI9CbdQnxvSOLV/3LbAhPhG8G4tG5YwxW7aQbT/YnBVLqek # CiLuN9/Wib7UYkYpeP1dAGhqMmPmIxrwCuxFMXhzARiiyLSKZhBHRCOv5WF8wkL5 # F7j+Cx8v+A6wUQBx09Oxb9mK6EDcjiaaSqlDSoq4WvvUWVphugFyoypKTa8XZM8H # qrs+jOyODFeRz6QOiei2FG0eswvSDIFMZt8mtFC5vutSSzIaGmD/yCDU/oMfoFwC # r7O85dVhhDnyagmp1wnQaePSehoekcnN87A4Zego/LM6sGua+3GYMR5qnKnMsKgr # wSJ8nPHGK30et4qfCqdYH0FK2EoRwTc/17C5FXV5FiMXQuEPuyMRqrUFj8Iv4AZc # MqvNfJvDHS6ZXrZv4a9rFY/LkOfupC/Zsd+p3QoT3CTicebaxEr/6TTOR9vFvw3k # InzNe4cc9Be4TtyamRA1mA== # =a85M # -----END PGP SIGNATURE----- # gpg: Signature made Thu 09 Jun 2022 02:04:13 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220609' of https://git.linaro.org/people/pmaydell/qemu-arm: (55 commits) target/arm: Add ID_AA64SMFR0_EL1 target/arm: Add isar_feature_aa64_sme target/arm: Export bfdotadd from vec_helper.c target/arm: Move expand_pred_h to vec_internal.h target/arm: Use expand_pred_b in mve_helper.c target/arm: Move expand_pred_b to vec_internal.h target/arm: Export sve contiguous ldst support functions target/arm: Split out load/store primitives to sve_ldst_internal.h target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el target/arm: Use uint32_t instead of bitmap for sve vq's target/arm: Merge aarch64_sve_zcr_get_valid_len into caller target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset target/arm: Hoist arm_is_el2_enabled check in sve_exception_el target/arm: Use el_is_in_host for sve_exception_el target/arm: Use el_is_in_host for sve_zcr_len_for_el target/arm: Add el_is_in_host target/arm: Remove fp checks from sve_exception_el target/arm: Remove route_to_el2 check from sve_exception_el linux-user/aarch64: Introduce sve_vq target/arm: Rename TBFLAG_A64 ZCR_LEN to VL ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-08Merge tag 'vfio-updates-20220608.0' of ↵Richard Henderson2-2/+10
https://gitlab.com/alex.williamson/qemu into staging VFIO updates 2022-06-08 * Fix spurious alignment warnings for TPM on unmap too (Eric Auger) # -----BEGIN PGP SIGNATURE----- # # iQJPBAABCAA5FiEEQvbATlQL0amee4qQI5ubbjuwiyIFAmKgtfQbHGFsZXgud2ls # bGlhbXNvbkByZWRoYXQuY29tAAoJECObm247sIsip8wP/1Fsj6X0rsdPz/mct5VS # aoTt+7jqo9b+7wHNetJsgt2t0hj3jzWbUgAzxeV9wA9K7kkqs7oiGY2eCzkfTAgt # Z/LlI6pJKVA1Z0xfbG3l2pldP+NgiFSIj3DwH7/ujw5uOAsPMsC51hnCva/V0EeZ # FzixVZlWaIsNG4BOeNtEX7ZOCICJfyo6c/4RnxYI94cgXbhwmzo4ljvkA/qkR8Mm # qM9082flXLQA92F/QHeA/2Wj7J1XTUzDQYRrhB1SXWbtJabp2uKhMmas6ZykBtXw # L3RPR4iVeRF0zzKhPEgl9pPnItO7qreX1/60KSWNOlQfLwGCQgqyKUSwDr4Qcmmz # vGmdl5pf0JckaIIps+OeM257OIXmoY7jfVcOaJJmM4e2RxtYFMTk+eyo33qUo76c # LWnGiucsCIU9bXJHtarmqmfOxxRDaAAK0HWufNox+BVbVLpKK4YG+Zp+zCYbkrrh # pAeATeJYwkKPbCb4OAX+/At8jiZxrfGkTDMGrwuobxEPILb6JmdYoQ1MXJhzNOKg # wfxo62SBuWFs2Rio4N/ZkxUIvP7aU6D1xEXXs72yR9waoLuQQmucXjHqJh3UZ/su # Ge/IywbKmWeo8ZRTklpIDmTKE/U1GSncain/D5NEtq0o/xKKgKQ6emL4059IklWo # LBdxfUewyv/qrTaWLI4I+/Xr # =VIGl # -----END PGP SIGNATURE----- # gpg: Signature made Wed 08 Jun 2022 07:45:08 AM PDT # gpg: using RSA key 42F6C04E540BD1A99E7B8A90239B9B6E3BB08B22 # gpg: issuer "alex.williamson@redhat.com" # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [undefined] # gpg: aka "Alex Williamson <alex@shazbot.org>" [undefined] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [undefined] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * tag 'vfio-updates-20220608.0' of https://gitlab.com/alex.williamson/qemu: vfio/common: remove spurious warning on vfio_listener_region_del Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-08target/arm: Add ID_AA64SMFR0_EL1Richard Henderson3-6/+34
This register is allocated from the existing block of id registers, so it is already RES0 for cpus that do not implement SME. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Add isar_feature_aa64_smeRichard Henderson1-0/+5
This will be used for implementing FEAT_SME. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Export bfdotadd from vec_helper.cRichard Henderson2-1/+14
We will need this over in sme_helper.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move expand_pred_h to vec_internal.hRichard Henderson3-29/+33
Move the data to vec_helper.c and the inline to vec_internal.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Use expand_pred_b in mve_helper.cRichard Henderson1-3/+3
Use the function instead of the array directly. Because the function performs its own masking, via the uint8_t parameter, we need to do nothing extra within the users: the bits above the first 2 (_uh) or 4 (_uw) will be discarded by assignment to the local bmask variables, and of course _uq uses the entire uint64_t result. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move expand_pred_b to vec_internal.hRichard Henderson2-10/+7
Put the inline function near the array declaration. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Export sve contiguous ldst support functionsRichard Henderson2-70/+111
Export all of the support functions for performing bulk fault analysis on a set of elements at contiguous addresses controlled by a predicate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Split out load/store primitives to sve_ldst_internal.hRichard Henderson2-106/+128
Begin creation of sve_ldst_internal.h by moving the primitives that access host and tlb memory. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_elRichard Henderson5-10/+19
This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g' and then adding a function comment. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Use uint32_t instead of bitmap for sve vq'sRichard Henderson6-105/+75
The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing zeros as required to find the result. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Merge aarch64_sve_zcr_get_valid_len into callerRichard Henderson2-30/+11
This function is used only once, and will need modification for Streaming SVE mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Do not use aarch64_sve_zcr_get_valid_len in resetRichard Henderson1-2/+1
We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Hoist arm_is_el2_enabled check in sve_exception_elRichard Henderson1-8/+5
This check is buried within arm_hcr_el2_eff(), but since we have to have the explicit check for CPTR_EL2.TZ, we might as well just check it once at the beginning of the block. Once this is done, we can test HCR_EL2.{E2H,TGE} directly, rather than going through arm_hcr_el2_eff(). Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Use el_is_in_host for sve_exception_elRichard Henderson1-3/+2
The ARM pseudocode function CheckNormalSVEEnabled uses this predicate now, and I think it's a bit clearer. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Use el_is_in_host for sve_zcr_len_for_elRichard Henderson1-2/+1
The ARM pseudocode function NVL uses this predicate now, and I think it's a bit clearer. Simplify the pseudocode condition by noting that IsInHost is always false for EL1. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Add el_is_in_hostRichard Henderson2-0/+30
This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Remove fp checks from sve_exception_elRichard Henderson1-39/+19
Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Remove route_to_el2 check from sve_exception_elRichard Henderson1-2/+1
We handle this routing in raise_exception. Promoting the value early means that we can't directly compare FPEXC_EL and SVEEXC_EL. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08linux-user/aarch64: Introduce sve_vqRichard Henderson3-8/+25
Add an interface function to extract the digested vector length rather than the raw zcr_el[1] value. This fixes an incorrect return from do_prctl_set_vl where we didn't take into account the set of vector lengths supported by the cpu. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Rename TBFLAG_A64 ZCR_LEN to VLRichard Henderson6-6/+7
With SME, the vector length does not only come from ZCR_ELx. Comment that this is either NVL or SVL, like the pseudocode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220607203306.657998-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Pass CPUARMState to arm_ld[lq]_ptwRichard Henderson1-14/+9
The use of ARM_CPU to recover env from cs calls object_class_dynamic_cast, which shows up on the profile. This is pointless, because all callers already have env, and the reverse operation, env_cpu, is only pointer arithmetic. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-29-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.cRichard Henderson2-32/+28
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-28-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.cRichard Henderson2-26/+24
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-27-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move regime_translation_disabled to ptw.cRichard Henderson3-65/+46
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-26-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move regime_ttbr to ptw.cRichard Henderson3-17/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-25-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move regime_is_user to ptw.cRichard Henderson3-25/+22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-24-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move ap_to_tw_prot etc to ptw.cRichard Henderson3-87/+81
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-23-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move aa32_va_parameters to ptw.cRichard Henderson3-67/+64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-22-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move check_s2_mmu_setup to ptw.cRichard Henderson3-72/+70
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-21-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move get_S1prot, get_S2prot to ptw.cRichard Henderson3-131/+128
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-20-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move arm_pamax, pamax_map into ptw.cRichard Henderson3-27/+25
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-19-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.cRichard Henderson2-24/+26
These functions are used for both page table walking and for deciding what format in which to deliver exception results. Since ptw.c is only present for system mode, put the functions into tlb_helper.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-18-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move arm_{ldl,ldq}_ptw to ptw.cRichard Henderson3-160/+154
Move the ptw load functions, plus 3 common subroutines: S1_ptw_translate, ptw_attrs_are_device, and regime_translation_big_endian. This also allows get_phys_addr_lpae to become static again. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-17-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move get_phys_addr_lpae to ptw.cRichard Henderson3-408/+429
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-16-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move combine_cacheattrs and subroutines to ptw.cRichard Henderson3-221/+221
There are a handful of helpers for combine_cacheattrs that we can move at the same time as the main entry point. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move get_level1_table_address to ptw.cRichard Henderson3-27/+26
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-14-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move m_is_{ppb,system}_region to ptw.cRichard Henderson3-18/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move v8m_security_lookup to ptw.cRichard Henderson2-123/+126
This function has one private helper, v8m_is_sau_exempt, so move that at the same time. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move pmsav7_use_background_region to ptw.cRichard Henderson3-21/+21
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move pmsav8_mpu_lookup to ptw.cRichard Henderson3-142/+143
This is the final user of get_phys_addr_pmsav7_default within helper.c, so make it static within ptw.c. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move get_phys_addr_pmsav8 to ptw.cRichard Henderson3-80/+77
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-08target/arm: Move get_phys_addr_pmsav7 to ptw.cRichard Henderson3-196/+198
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-02-01 05:16:45 +0000