| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-09-01 | hw/arm/armv7m: Create input clocks | Peter Maydell | 2 | -0/+29 |
| 2021-09-01 | hw/timer/armv7m_systick: Add input clocks | Peter Maydell | 2 | -2/+15 |
| 2021-09-01 | hw/timer/armv7m_systick: Add usual QEMU interface comment | Peter Maydell | 1 | -0/+7 |
| 2021-09-01 | arm: Move system PPB container handling to armv7m | Peter Maydell | 4 | -145/+107 |
| 2021-09-01 | arm: Move systick device creation from NVIC to ARMv7M object | Peter Maydell | 4 | -77/+137 |
| 2021-09-01 | arm: Move M-profile RAS register block into its own device | Peter Maydell | 8 | -57/+148 |
| 2021-09-01 | tests/arm-cpu-features: Add A64FX processor related tests | Shuuichirou Ishii | 1 | -0/+13 |
| 2021-09-01 | hw/arm/virt: target-arm: Add A64FX processor support to virt machine | Shuuichirou Ishii | 2 | -0/+2 |
| 2021-09-01 | target-arm: Add support for Fujitsu A64FX | Shuuichirou Ishii | 1 | -0/+48 |
| 2021-09-01 | target/arm: Enable MVE in Cortex-M55 | Peter Maydell | 1 | -5/+2 |
| 2021-09-01 | target/arm: Implement MVE VRINT insns | Peter Maydell | 4 | -0/+93 |
| 2021-09-01 | target/arm: Implement MVE VCVT between single and half precision | Peter Maydell | 4 | -0/+108 |
| 2021-09-01 | target/arm: Implement MVE VCVT with specified rounding mode | Peter Maydell | 4 | -0/+105 |
| 2021-09-01 | target/arm: Implement MVE VCVT between fp and integer | Peter Maydell | 2 | -0/+39 |
| 2021-09-01 | target/arm: Implement MVE VCVT between floating and fixed point | Peter Maydell | 4 | -0/+82 |
| 2021-09-01 | target/arm: Implement MVE fp scalar comparisons | Peter Maydell | 4 | -24/+131 |
| 2021-09-01 | target/arm: Implement MVE fp vector comparisons | Peter Maydell | 4 | -6/+137 |
| 2021-09-01 | target/arm: Implement MVE FP max/min across vector | Peter Maydell | 4 | -6/+102 |
| 2021-09-01 | softfloat: Remove assertion preventing silencing of NaN in default-NaN mode | Peter Maydell | 1 | -1/+0 |
| 2021-09-01 | target/arm: Implement MVE fp-with-scalar VFMA, VFMAS | Peter Maydell | 4 | -3/+56 |
| 2021-09-01 | target/arm: Implement MVE scalar fp insns | Peter Maydell | 4 | -6/+85 |
| 2021-09-01 | target/arm: Implement MVE VMAXNMA and VMINNMA | Peter Maydell | 4 | -0/+42 |
| 2021-09-01 | target/arm: Implement MVE VCMUL and VCMLA | Peter Maydell | 4 | -8/+139 |
| 2021-09-01 | target/arm: Implement MVE VFMA and VFMS | Peter Maydell | 4 | -0/+48 |
| 2021-09-01 | target/arm: Implement MVE VCADD | Peter Maydell | 4 | -1/+57 |
| 2021-09-01 | target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM | Peter Maydell | 4 | -0/+42 |
| 2021-09-01 | target/arm: Implement MVE VADD (floating-point) | Peter Maydell | 6 | -6/+76 |
| 2021-09-01 | hw: Add compat machines for 6.2 | Yanan Wang | 9 | -6/+71 |
| 2021-09-01 | hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans | Philippe Mathieu-Daudé | 1 | -95/+106 |
| 2021-09-01 | hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix | Philippe Mathieu-Daudé | 1 | -6/+6 |
| 2021-09-01 | hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases | Philippe Mathieu-Daudé | 3 | -9/+7 |
| 2021-09-01 | tests: Remove uses of deprecated raspi2/raspi3 machine names | Philippe Mathieu-Daudé | 7 | -32/+32 |
| 2021-09-01 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210... | Peter Maydell | 24 | -1381/+1240 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson | 2 | -61/+26 |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson | 2 | -210/+57 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson | 1 | -65/+60 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson | 1 | -76/+70 |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson | 1 | -13/+6 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson | 1 | -28/+19 |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson | 3 | -66/+132 |
| 2021-09-01 | target/riscv: Fix hgeie, hgeip | Richard Henderson | 1 | -18/+8 |
| 2021-09-01 | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation | Richard Henderson | 1 | -8/+15 |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson | 1 | -18/+20 |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson | 1 | -15/+10 |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson | 1 | -2/+12 |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson | 3 | -202/+125 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_unary | Richard Henderson | 2 | -23/+15 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVB | Richard Henderson | 2 | -233/+234 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVM | Richard Henderson | 2 | -127/+127 |
| 2021-09-01 | target/riscv: Use gen_arith for mulh and mulhu | Richard Henderson | 1 | -22/+18 |
