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2021-10-01linux-user/sparc: Implement setup_sigtrampRichard Henderson2-14/+30
Create and record the two signal trampolines. Use them when the guest does not use SA_RESTORER. Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-24-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/sh4: Implement setup_sigtrampRichard Henderson2-18/+24
Create and record the two signal trampolines. Use them when the guest does not use SA_RESTORER. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-23-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/s390x: Implement setup_sigtrampRichard Henderson2-8/+18
Create and record the two signal trampolines. Use them when the guest does not use SA_RESTORER. Cc: qemu-s390x@nongnu.org Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-22-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/riscv: Implement setup_sigtrampRichard Henderson2-9/+15
Create and record the rt signal trampoline. This fixes a bug wrt libgcc fallback unwinding. It expects the stack pointer to point to the siginfo_t, whereas we had inexplicably placed our private signal trampoline at the start of the signal frame instead of the end. Now moot because we have removed it from the stack frame entirely. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-21-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/ppc: Implement setup_sigtrampRichard Henderson2-16/+20
Create and record the two signal trampolines. Cc: qemu-ppc@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-20-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/ppc: Simplify encode_trampolineRichard Henderson1-4/+2
The sigret parameter is never 0, and even if it was the encoding of the LI instruction would still work. Reported-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-19-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/openrisc: Implement setup_sigtrampRichard Henderson2-8/+16
Create and record the rt signal trampoline. Reviewed-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/nios2: Document non-use of setup_sigtrampRichard Henderson1-0/+3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/mips: Implement setup_sigtrampRichard Henderson3-10/+27
Create and record the two signal trampolines. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-16-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/mips: Tidy install_sigtrampRichard Henderson1-4/+1
The return value is constant 0, and unused as well -- change to void. Drop inline marker. Change tramp type to uint32_t* for clarity. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/microblaze: Implement setup_sigtrampRichard Henderson2-7/+19
Create and record the rt signal trampoline. Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-14-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/m68k: Implement setup_sigtrampRichard Henderson2-25/+24
Create and record the two signal trampolines. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-13-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/x86_64: Raise SIGSEGV if SA_RESTORER not setRichard Henderson1-6/+5
This has been a fixme for some time. The effect of returning -EFAULT from the kernel code is to raise SIGSEGV. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-12-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/i386: Implement setup_sigtrampRichard Henderson3-18/+43
Create and record the two signal trampolines. Use them when the guest does not use SA_RESTORER. Note that x86_64 does not use this code. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-11-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/hppa: Document non-use of setup_sigtrampRichard Henderson1-0/+14
We cannot use a raw sigtramp page for hppa, but must wait for full vdso support. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-10-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/hexagon: Implement setup_sigtrampRichard Henderson2-2/+19
Continue to initialize the words on the stack, as documented. However, use the off-stack trampoline. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-9-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/cris: Implement setup_sigtrampRichard Henderson2-8/+23
Split out setup_sigreturn so that we can continue to initialize the words on the stack, as documented. However, use the off-stack trampoline. Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/alpha: Implement setup_sigtrampRichard Henderson2-14/+21
Create and record the two signal trampolines. Use them when the guest does not use ka_restorer. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/arm: Implement setup_sigtrampRichard Henderson2-71/+110
Mirror what the kernel does in arch/arm/kernel/signal.h, using the old sigframe struct in the rt sigframe struct. Update the trampoline code to match the kernel: this uses sp-relative accesses rather than pc-relative. Copy the code into frame->retcode from the trampoline page. This minimises the different cases wrt arm vs thumb vs fdpic. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210929130553.121567-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/arm: Drop "_v2" from symbols in signal.cRichard Henderson1-70/+45
Since we no longer support "v1", there's no need to distinguish "v2". Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/arm: Drop v1 signal framesRichard Henderson1-216/+4
Version 2 signal frames are used from 2.6.12 and since cbc14e6f286, we have set UNAME_MINIMUM_RELEASE to 2.6.32. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user/aarch64: Implement setup_sigtrampRichard Henderson2-13/+23
Create and record the rt signal trampoline. Use it when the guest does not use SA_RESTORER. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-01linux-user: Add infrastructure for a signal trampoline pageRichard Henderson3-0/+27
Allocate a page to hold the signal trampoline(s). Invoke a guest-specific hook to fill in the contents of the page before marking it read-execute again. Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210929130553.121567-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-30Merge remote-tracking branch ↵Peter Maydell108-447/+3806
'remotes/pmaydell/tags/pull-target-arm-20210930' into staging target-arm queue: * allwinner-h3: Switch to SMC as PSCI conduit * arm: tcg: Adhere to SMCCC 1.3 section 5.2 * xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices * gdbstub related code cleanups * Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML * Use _init vs _new convention in bus creation function names * sabrelite: Connect SPI flash CS line to GPIO3_19 # gpg: Signature made Thu 30 Sep 2021 16:11:20 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210930: (22 commits) hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 ide: Rename ide_bus_new() to ide_bus_init() qbus: Rename qbus_create() to qbus_new() qbus: Rename qbus_create_inplace() to qbus_init() pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML target/arm: Move gdbstub related code out of helper.c target/arm: Fix coding style issues in gdbstub code in helper.c configs: Don't include 32-bit-only GDB XML in aarch64 linux configs docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage hw/arm: xlnx-zcu102: Add Xilinx eFUSE device hw/arm: xlnx-zcu102: Add Xilinx BBRAM device hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device hw/nvram: Introduce Xilinx battery-backed ram hw/nvram: Introduce Xilinx ZynqMP eFuse device hw/nvram: Introduce Xilinx Versal eFuse device hw/nvram: Introduce Xilinx eFuse QOM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-30Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ↵Peter Maydell64-38/+1397
staging * SGX implementation for x86 * Miscellaneous bugfixes * Fix dependencies from ROMs to qtests # gpg: Signature made Thu 30 Sep 2021 14:30:35 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (33 commits) meson_options.txt: Switch the default value for the vnc option to 'auto' build-sys: add HAVE_IPPROTO_MPTCP memory: Add tracepoint for dirty sync memory: Name all the memory listeners target/i386: Fix memory leak in sev_read_file_base64() tests: qtest: bios-tables-test depends on the unpacked edk2 ROMs meson: unpack edk2 firmware even if --disable-blobs target/i386: Add the query-sgx-capabilities QMP command target/i386: Add HMP and QMP interfaces for SGX docs/system: Add SGX documentation to the system manual sgx-epc: Add the fill_device_info() callback support i440fx: Add support for SGX EPC q35: Add support for SGX EPC i386: acpi: Add SGX EPC entry to ACPI tables i386/pc: Add e820 entry for SGX EPC section(s) hw/i386/pc: Account for SGX EPC sections when calculating device memory hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly Adjust min CPUID level to 0x12 when SGX is enabled i386: Propagate SGX CPUID sub-leafs to KVM i386: kvm: Add support for exposing PROVISIONKEY to guest ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-30Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210930' ↵Peter Maydell35-445/+741
into staging ppc patch queue for 2021-09-30 Here's the next batch of ppc related patches for qemu-6.2. Highlights are: * Fixes for several TCG math instructions from the El Dorado Institute * A number of improvements to the powernv machine type * Support for a new DEVICE_UNPLUG_GUEST_ERROR QAPI event from Daniel Barboza * Support for the new FORM2 PAPR NUMA representation. This allows more specific NUMA distances, as well as asymmetric configurations * Fix for 64-bit decrementer (used on MicroWatt CPUs) * Assorted fixes and cleanups * A number of updates to MAINTAINERS Note that the DEVICE_UNPLUG_GUEST_ERROR stuff includes changes to files outside my normal area, but has suitable Acks. The MAINTAINERS updates are mostly about marking minor platforms unmaintained / orphaned, and moving some pieces away from myself and Greg. As we move onto other projects, we're going to need to drop more of the ppc maintainership, though we're hoping we can avoid too abrupt a change. # gpg: Signature made Thu 30 Sep 2021 06:42:41 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.2-20210930: (44 commits) MAINTAINERS: Demote sPAPR from "Supported" to "Maintained" MAINTAINERS: Add information for OpenPIC MAINTAINERS: Remove David & Greg as reviewers/co-maintainers of powernv MAINTAINERS: Orphan obscure ppc platforms MAINTAINERS: Remove David & Greg as reviewers for a number of boards MAINTAINERS: Remove machine specific files from ppc TCG CPUs entry spapr/xive: Fix kvm_xive_source_reset trace event spapr_numa.c: fixes in spapr_numa_FORM2_write_rtas_tables() hw/intc: openpic: Clean up the styles hw/intc: openpic: Drop Raven related codes hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset target/ppc: Fix 64-bit decrementer target/ppc: Convert debug to trace events (decrementer and IRQ) spapr_numa.c: handle auto NUMA node with no distance info spapr_numa.c: FORM2 NUMA affinity support spapr: move FORM1 verifications to post CAS spapr_numa.c: rename numa_assoc_array to FORM1_assoc_array spapr_numa.c: parametrize FORM1 macros spapr_numa.c: scrap 'legacy_numa' concept spapr_numa.c: split FORM1 code into helpers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-30meson_options.txt: Switch the default value for the vnc option to 'auto'Thomas Huth1-1/+1
There is no reason why VNC should always be enabled and not be set to the default value. We already switched the setting in the "configure" script in commit 3a6a1256d4 ("configure: Allow vnc to get disabled with --without-default-features"), so let's do that in meson_options.txt now, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210903081358.956267-3-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30build-sys: add HAVE_IPPROTO_MPTCPMarc-André Lureau4-5/+7
The QAPI schema shouldn't rely on C system headers #define, but on configure-time project #define, so we can express the build condition in a C-independent way. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20210907121943.3498701-3-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30memory: Add tracepoint for dirty syncPeter Xu2-0/+3
Trace at memory_region_sync_dirty_bitmap() for log_sync() or global_log_sync() on memory regions. One trace line should suffice when it finishes, so as to estimate the time used for each log sync process. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20210817013706.30986-1-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30memory: Name all the memory listenersPeter Xu19-4/+33
Provide a name field for all the memory listeners. It can be used to identify which memory listener is which. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20210817013553.30584-2-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30target/i386: Fix memory leak in sev_read_file_base64()Peter Maydell1-1/+1
In sev_read_file_base64() we call g_file_get_contents(), which allocates memory for the file contents. We then base64-decode the contents (which allocates another buffer for the decoded data), but forgot to free the memory for the original file data. Use g_autofree to ensure that the file data is freed. Fixes: Coverity CID 1459997 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210820165650.2839-1-peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30tests: qtest: bios-tables-test depends on the unpacked edk2 ROMsPaolo Bonzini2-4/+5
Skip the test if bzip2 is not available, and run it after they are uncompressed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210923105529.3845741-2-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30meson: unpack edk2 firmware even if --disable-blobsPaolo Bonzini3-11/+11
The edk2 firmware blobs are needed to run bios-tables-test. Unpack them if any UEFI-enabled target is selected, so that the test can run. This is a bit more than is actually necessary, since bios-tables-test does not run for all UEFI-enabled targets, but it is the easiest way to write this logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210923105529.3845741-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30target/i386: Add the query-sgx-capabilities QMP commandYang Zhong6-0/+97
Libvirt can use query-sgx-capabilities to get the host sgx capabilities to decide how to allocate SGX EPC size to VM. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210910102258.46648-3-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30target/i386: Add HMP and QMP interfaces for SGXYang Zhong8-0/+136
The QMP and HMP interfaces can be used by monitor or QMP tools to retrieve the SGX information from VM side when SGX is enabled on Intel platform. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210910102258.46648-2-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30docs/system: Add SGX documentation to the system manualSean Christopherson2-0/+166
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-34-yang.zhong@intel.com> [Convert to reStructuredText, and adopt the standard === --- ~~~ headings suggested for example by Linux. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30sgx-epc: Add the fill_device_info() callback supportYang Zhong3-4/+56
Since there is no fill_device_info() callback support, and when we execute "info memory-devices" command in the monitor, the segfault will be found. This patch will add this callback support and "info memory-devices" will show sgx epc memory exposed to guest. The result as below: qemu) info memory-devices Memory device [sgx-epc]: "" memaddr: 0x180000000 size: 29360128 memdev: /objects/mem1 Memory device [sgx-epc]: "" memaddr: 0x181c00000 size: 10485760 memdev: /objects/mem2 Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-33-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i440fx: Add support for SGX EPCSean Christopherson1-0/+1
Enable SGX EPC virtualization, which is currently only support by KVM. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-22-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30q35: Add support for SGX EPCSean Christopherson1-0/+1
Enable SGX EPC virtualization, which is currently only support by KVM. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-21-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: acpi: Add SGX EPC entry to ACPI tablesSean Christopherson1-0/+22
The ACPI Device entry for SGX EPC is essentially a hack whose primary purpose is to provide software with a way to autoprobe SGX support, e.g. to allow software to implement SGX support as a driver. Details on the individual EPC sections are not enumerated through ACPI tables, i.e. software must enumerate the EPC sections via CPUID. Furthermore, software expects to see only a single EPC Device in the ACPI tables regardless of the number of EPC sections in the system. However, several versions of Windows do rely on the ACPI tables to enumerate the address and size of the EPC. So, regardless of the number of EPC sections exposed to the guest, create exactly *one* EPC device with a _CRS entry that spans the entirety of all EPC sections (which are guaranteed to be contiguous in Qemu). Note, NUMA support for EPC memory is intentionally not considered as enumerating EPC NUMA information is not yet defined for bare metal. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-20-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386/pc: Add e820 entry for SGX EPC section(s)Sean Christopherson1-0/+4
Note that SGX EPC is currently guaranteed to reside in a single contiguous chunk of memory regardless of the number of EPC sections. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-19-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30hw/i386/pc: Account for SGX EPC sections when calculating device memorySean Christopherson2-1/+17
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX EPC above 4g ends. Use the helpers to adjust the device memory range if SGX EPC exists above 4g. For multiple virtual EPC sections, we just put them together physically contiguous for the simplicity because we don't support EPC NUMA affinity now. Once the SGX EPC NUMA support in the kernel SGX driver, we will support this in the future. Note that SGX EPC is currently hardcoded to reside above 4g. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-18-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordinglySean Christopherson1-1/+11
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL when the features are exposed to the guest. Our design is the SGX Launch Control bit will be unconditionally set in FEATURE_CONTROL, which is unlike host bios. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-17-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30Adjust min CPUID level to 0x12 when SGX is enabledSean Christopherson1-0/+5
SGX capabilities are enumerated through CPUID_0x12. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-16-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: Propagate SGX CPUID sub-leafs to KVMSean Christopherson1-0/+19
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are always present when SGX is supported, and enumerate SGX features and capabilities. Indices >=2 are directly correlated with the platform's EPC sections. Because the number of EPC sections is dynamic and user defined, the number of SGX sub-leafs is "NULL" terminated. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-15-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: kvm: Add support for exposing PROVISIONKEY to guestSean Christopherson3-1/+35
If the guest want to fully use SGX, the guest needs to be able to access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to support provisioning key to KVM guests. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-14-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: Update SGX CPUID info according to hardware/KVM/user inputSean Christopherson6-1/+170
Expose SGX to the guest if and only if KVM is enabled and supports virtualization of SGX. While the majority of ENCLS can be emulated to some degree, because SGX uses a hardware-based root of trust, the attestation aspects of SGX cannot be emulated in software, i.e. ultimately emulation will fail as software cannot generate a valid quote/report. The complexity of partially emulating SGX in Qemu far outweighs the value added, e.g. an SGX specific simulator for userspace applications can emulate SGX for development and testing purposes. Note, access to the PROVISIONKEY is not yet advertised to the guest as KVM blocks access to the PROVISIONKEY by default and requires userspace to provide additional credentials (via ioctl()) to expose PROVISIONKEY. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-13-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: Add feature control MSR dependency when SGX is enabledSean Christopherson1-0/+5
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible Launch Control. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-12-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRsSean Christopherson4-1/+58
On real hardware, on systems that supports SGX Launch Control, those MSRs are initialized to digest of Intel's signing key; on systems that don't support SGX Launch Control, those MSRs are not available but hardware always uses digest of Intel's signing key in EINIT. KVM advertises SGX LC via CPUID if and only if the MSRs are writable. Unconditionally initialize those MSRs to digest of Intel's signing key when CPU is realized and reset to reflect the fact. This avoids potential bug in case kvm_arch_put_registers() is called before kvm_arch_get_registers() is called, in which case guest's virtual SGX_LEPUBKEYHASH MSRs will be set to 0, although KVM initializes those to digest of Intel's signing key by default, since KVM allows those MSRs to be updated by Qemu to support live migration. Save/restore the SGX Launch Enclave Public Key Hash MSRs if SGX Launch Control (LC) is exposed to the guest. Likewise, migrate the MSRs if they are writable by the guest. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Kai Huang <kai.huang@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-11-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-30i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAXSean Christopherson2-0/+22
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating the platform's SGX capabilities that may be utilized by an enclave, e.g. whether or not an enclave can gain access to the provision key. Currently there are six capabilities: - INIT: set when the enclave has has been initialized by EINIT. Cannot be set by software, i.e. forced to zero in CPUID. - DEBUG: permits a debugger to read/write into the enclave. - MODE64BIT: the enclave runs in 64-bit mode - PROVISIONKEY: grants has access to the provision key - EINITTOKENKEY: grants access to the EINIT token key, i.e. the enclave can generate EINIT tokens - KSS: Key Separation and Sharing enabled for the enclave. Note that the entirety of CPUID.0x12.0x1, i.e. all registers, enumerates the allowed ATTRIBUTES (128 bits), but only bits 31:0 are directly exposed to the user (via FEAT_12_1_EAX). Bits 63:32 are currently all reserved and bits 127:64 correspond to the allowed XSAVE Feature Request Mask, which is calculated based on other CPU features, e.g. XSAVE, MPX, AVX, etc... and is not exposed to the user. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20210719112136.57018-10-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-01-15 22:08:01 +0000