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2018-02-09s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facilityDavid Hildenbrand4-0/+28
For now, the kernel does not properly indicate configured CPU subfunctions to the guest, but simply uses the host values (as support in KVM is still missing). That's why we missed to model the PTFF subfunctions that come with Multiple-epoch facility. Let's properly add these, along with a new feature group. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180205102935.14736-1-david@redhat.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/cpumodel: allow zpci features in qemu modelCornelia Huck2-1/+11
AEN and AIS can be provided unconditionally, ZPCI should be turned on manually. With -cpu qemu,zpci=on, the guest kernel can now successfully detect virtio-pci devices under tcg. Also fixup the order of the MSA_EXT_{3,4} flags while at it. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: wire up pci instructionsCornelia Huck4-0/+213
On s390x, pci support is implemented via a set of instructions (no mmio). Unfortunately, none of them are documented in the PoP; the code is based upon the existing implementation for KVM and the Linux zpci driver. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/sclp: fix event mask handlingChristian Borntraeger1-2/+2
commit 67915de9f038 ("s390x/event-facility: variable-length event masks") switched the sclp receive/send mask. This broke the sclp lm console. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Fixes: commit 67915de9f038 ("s390x/event-facility: variable-length event masks") Cc: Cornelia Huck <cohuck@redhat.com> Cc: Jason J. Herne <jjherne@linux.vnet.ibm.com> Cc: qemu-stable@nongnu.org Message-Id: <20180202094241.59537-1-borntraeger@de.ibm.com> Reviewed-by: Claudio Imbrenda <imbrenda@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: cache the common flic class in a central functionDavid Hildenbrand5-11/+23
This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/kvm: cache the kvm flic in a central functionDavid Hildenbrand1-5/+16
This avoids tons of conversions when handling interrupts. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: cache the qemu flic in a central functionDavid Hildenbrand4-10/+22
This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09configure: s390x supports mttcg nowDavid Hildenbrand1-0/+1
s390x is ready. Most likely we are missing some pieces, but it should already be in pretty good shape now. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: remove SMP warningDavid Hildenbrand1-4/+0
We should be pretty good in shape now. Floating interrupts are working and atomic instructions should be atomic. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: STSI overhaulDavid Hildenbrand2-103/+131
Current STSI implementation is a mess, so let's rewrite it. Problems fixed by this patch: 1) The order of exceptions/when recognized is wrong. 2) We have to store to virtual address space, not absolute. 3) Alignment check of the block is missing. 3) The SMP information is not indicated. While at it: a) Make the code look nicer - get rid of nesting levels - use struct initialization instead of initializing to zero - rename a misspelled field and rename function code defines - use a union and have only one write statement - use cpu_to_beX() b) Indicate the VM name/extended name + UUID just like KVM does c) Indicate that all LPAR CPUs we fake are dedicated d) Add a comment why we fake being a KVM guest e) Give our guest as default the name "TCGguest" f) Fake the same CPU information we have in our Guest for all layers While at it, get rid of "potential_page_fault()" by forwarding the retaddr properly. The result is best verified by looking at "/proc/sysinfo" in the guest when specifying on the qemu command line -uuid "74738ff5-5367-5958-9aee-98fffdcd1876" \ -name "extra long guest name" Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x: fix size + content of STSI blocksDavid Hildenbrand3-27/+33
All blocks are 4k in size, which is only true for two of them right now. Also some reserved fields were wrong, fix it and convert all reserved fields to u8. This also fixes the LPAR part output in /proc/sysinfo under TCG. (for now, everything was indicated as 0) While at it, introduce typedefs for these structs and use them in TCG/KVM code. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: optimize CPU wakeup for TCGDavid Hildenbrand3-7/+33
Kicking all CPUs on every floating interrupt is far from efficient. Let's optimize it at least a little bit. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: implement qemu_s390_clear_io_flic()David Hildenbrand1-2/+29
Now that we have access to the io interrupts, we can implement clear_io_irq() for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: implement TEST PENDING INTERRUPTIONDavid Hildenbrand4-0/+64
Use s390_cpu_virt_mem_write() so we can actually revert what we did (re-inject the dequeued IO interrupt). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: make floating interrupts on TCG actually floatingDavid Hildenbrand6-152/+212
Move floating interrupt handling into the flic. Floating interrupts will now be considered by all CPUs, not just CPU #0. While at it, convert I/O interrupts to use a list and make sure we properly consider I/O sub-classes in s390_cpu_has_io_int(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: tolerate wrong wakeups due to floating interruptsDavid Hildenbrand1-0/+5
This is a preparation for floating interrupt support and only applies to MTTCG, single threaded TCG works just fine. If a floating interrupt wakes up a VCPU and the CPU thinks it can run (clearing cs->halted), at the point where the interrupt would be delivered, already another VCPU might have picked up the interrupt, resulting in a wakeup without an interrupt (executing wrong code). It is wrong to let the VCPU continue to execute (the WAIT PSW). Instead, we have to put the VCPU back to sleep. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: no need to call s390_io_interrupt() from flicDavid Hildenbrand1-1/+2
We can directly call the right function. Suggested-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: factor out injection of floating interruptsDavid Hildenbrand8-116/+123
Let the flic device handle it internally. This will allow us to later on store floating interrupts in the flic for the TCG case. This now also simplifies kvm.c. All that's left is the fallback interface for floating interrupts, which is now triggered directly via the flic in case anything goes wrong. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: simplify machine check handlingDavid Hildenbrand4-47/+12
We currently only support CRW machine checks. This is a preparation for real floating interrupt support. Get rid of the queue and handle it via the bit INTERRUPT_MCHK. We don't rename it for now, as it will be soon gone (when moving crw machine checks into the flic). Please note that this is the same way also KVM handles it: only one instance of a machine check can be pending at a time. So no need for a queue. While at it, make sure we try to deliver only if env->cregs[14] actually indicates that CRWs are accepted. Drop two unused defines on the way (we already have PSW_MASK_...). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: simplify lookup of flicDavid Hildenbrand1-5/+3
We can simply search for an object of our common type. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: simplify flic initializationDavid Hildenbrand3-23/+5
This makes it clearer, which device is used for which accelerator. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: deliver multiple interrupts in a rowDavid Hildenbrand1-4/+16
We have to consider all deliverable interrupts. We now have to take care of the special scenario, where we first inject an interrupt with a WAIT PSW, followed by a !WAIT PSW. (very unlikely but possible) Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-2-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09Fix configure for s390 qemu on alpine and other busybox environmentsAlice Frosi1-2/+2
In alpine docker image the qemu-system-s390x build is broken and it throws this error: qemu-system-s390x: Initialization of device s390-ipl failed: could not load bootloader 's390-ccw.img' The grep command of busybox uses regex. This fails on binary data (e.g. stops on every \0), so it does not identify the string BiGeNdIaN in the test case big/little. Therefore, it assumes that the architecture is little endian. This fix solves the grep problem by printing the content of TMPO with strings Signed-off-by: Alice Frosi <alice@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> [some changes to patch description, add -a option to strings] Message-Id: <20180130133828.77336-2-borntraeger@de.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09Drop superfluous includes of qapi-types.h and test-qapi-types.hMarkus Armbruster35-36/+0
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-4-armbru@redhat.com>
2018-02-09Clean up includesMarkus Armbruster30-51/+9
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes, with the change to target/s390x/gen-features.c manually reverted, and blank lines around deletions collapsed. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-3-armbru@redhat.com>
2018-02-09Use #include "..." for our own headers, <...> for othersMarkus Armbruster19-27/+20
System headers should be included with <...>, our own headers with "...". Offenders tracked down with an ugly, brittle and probably buggy Perl script. Previous iteration was commit a9c94277f0. Delete inclusions of "string.h" and "strings.h" instead of fixing them to <string.h> and <strings.h>, because we always include these via osdep.h. Put the cleaned up system header includes first. While there, separate #include from file comment with exactly one blank line. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20180201111846.21846-2-armbru@redhat.com>
2018-02-09vnc: use stubs for CONFIG_VNC=n dummy functionsGerd Hoffmann3-21/+22
Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20180202064546.21746-1-kraxel@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-02-08Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180208' into stagingPeter Maydell25-495/+6969
tcg generic vectors # gpg: Signature made Thu 08 Feb 2018 16:47:16 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20180208: tcg/aarch64: Add vector operations tcg/i386: Add vector operations target/arm: Use vector infrastructure for aa64 orr/bic immediate target/arm: Use vector infrastructure for aa64 multiplies target/arm: Use vector infrastructure for aa64 compares target/arm: Use vector infrastructure for aa64 constant shifts target/arm: Use vector infrastructure for aa64 dup/movi target/arm: Use vector infrastructure for aa64 mov/not/neg target/arm: Use vector infrastructure for aa64 add/sub/logic target/arm: Align vector registers tcg/optimize: Handle vector opcodes during optimize tcg: Add generic vector helpers with a scalar operand tcg: Add generic helpers for saturating arithmetic tcg: Add generic vector ops for multiplication tcg: Add generic vector ops for comparisons tcg: Add generic vector ops for constant shifts tcg: Add generic vector expanders tcg: Standardize integral arguments to expanders tcg: Add types and basic operations for host vectors tcg: Allow multiple word entries into the constant pool Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-08tcg/aarch64: Add vector operationsRichard Henderson3-47/+569
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg/i386: Add vector operationsRichard Henderson3-54/+987
The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and adjusts how all instructions should be encoded. Given the relatively narrow 2 year window between possible to support and desirable to support, and to vastly simplify code maintainence, I am only planning to support AVX1 and later cpus. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 orr/bic immediateRichard Henderson1-23/+5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 multipliesRichard Henderson1-25/+129
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 comparesRichard Henderson1-34/+59
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 constant shiftsRichard Henderson1-73/+346
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 dup/moviRichard Henderson1-48/+33
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 mov/not/negRichard Henderson1-6/+36
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Use vector infrastructure for aa64 add/sub/logicRichard Henderson1-72/+128
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08target/arm: Align vector registersRichard Henderson1-1/+1
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg/optimize: Handle vector opcodes during optimizeRichard Henderson1-73/+77
Trivial move and constant propagation. Some identity and constant function folding, but nothing that requires knowledge of the size of the vector element. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector helpers with a scalar operandRichard Henderson4-2/+617
Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic helpers for saturating arithmeticRichard Henderson4-0/+390
No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector ops for multiplicationRichard Henderson10-0/+111
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector ops for comparisonsRichard Henderson9-0/+255
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector ops for constant shiftsRichard Henderson10-0/+575
Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add generic vector expandersRichard Henderson13-18/+2024
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Standardize integral arguments to expandersRichard Henderson2-29/+29
Some functions use intN_t arguments, some use uintN_t, some just used "unsigned". To aid putting function pointers in tables, we need consistency. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Add types and basic operations for host vectorsRichard Henderson7-6/+543
Nothing uses or enables them yet. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08tcg: Allow multiple word entries into the constant poolRichard Henderson1-21/+92
This will be required for storing vector constants. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-02-08Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into ↵Peter Maydell33-829/+3580
staging # gpg: Signature made Thu 08 Feb 2018 01:29:22 GMT # gpg: using RSA key CA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/staging-pull-request: docs: Add docs/devel/testing.rst qapi: Add NVMe driver options to the schema docs: Add section for NVMe VFIO driver block: Move NVMe constants to a separate header qemu-img: Map bench buffer block/nvme: Implement .bdrv_(un)register_buf block: Introduce buf register API block: Add VFIO based NVMe driver util: Introduce vfio helpers stubs: Add stubs for ram block API curl: convert to CoQueue coroutine-lock: make qemu_co_enter_next thread-safe coroutine-lock: convert CoQueue to use QemuLockable lockable: add QemuLockable test-coroutine: add simple CoMutex test docker: change Fedora base image to fedora:27 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-08Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into ↵Peter Maydell1-0/+1
staging # gpg: Signature made Wed 07 Feb 2018 17:00:12 GMT # gpg: using RSA key 7DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/bitmaps-pull-request: hbitmap: fix missing restore count when finish deserialization Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-12-28 02:42:29 +0000