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2022-06-09tests: acpi: update expected DSDT.pvpanic-isa blobIgor Mammedov2-1/+0
@@ -145,6 +145,37 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Name (_ADR, 0x001F0000) // _ADR: Address OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + Device (PEVT) + { + Name (_HID, "QEMU0001") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0505, // Range Minimum + 0x0505, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + }) + OperationRegion (PEOR, SystemIO, 0x0505, One) + Field (PEOR, ByteAcc, NoLock, Preserve) + { + PEPT, 8 + } + + Name (_STA, 0x0F) // _STA: Status + Method (RDPT, 0, NotSerialized) + { + Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */ + Return (Local0) + } + + Method (WRPT, 1, NotSerialized) + { + PEPT = Arg0 + } + } + Device (KBD) { Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID @@ -3246,40 +3277,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) } } - Scope (\_SB.PCI0.ISA) - { - Device (PEVT) - { - Name (_HID, "QEMU0001") // _HID: Hardware ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x0505, // Range Minimum - 0x0505, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - }) - OperationRegion (PEOR, SystemIO, 0x0505, One) - Field (PEOR, ByteAcc, NoLock, Preserve) - { - PEPT, 8 - } - - Name (_STA, 0x0F) // _STA: Status - Method (RDPT, 0, NotSerialized) - { - Local0 = PEPT /* \_SB_.PCI0.ISA_.PEVT.PEPT */ - Return (Local0) - } - - Method (WRPT, 1, NotSerialized) - { - PEPT = Arg0 - } - } - } - Scope (\_SB) { Scope (PCI0) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-30-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AMLIgor Mammedov3-46/+42
.. and clean up not longer needed conditionals in DSTD build code pvpanic-isa AML will be fetched and included when ISA bridge will build its own AML code (including attached devices). Expected AML change: the device under separate _SB.PCI0.ISA scope is moved directly under Device(ISA) node. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-29-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: add pvpanic-isa: testcaseIgor Mammedov1-0/+12
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-28-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: white-lists expected DSDT.pvpanic-isa blobIgor Mammedov2-0/+1
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-27-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: update expected blobsIgor Mammedov2-1/+0
@@ -145,6 +145,23 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) { Name (_ADR, 0x001F0000) // _ADR: Address OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + Device (SMC) + { + Name (_HID, EisaId ("APP0001")) // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0300, // Range Minimum + 0x0300, // Range Maximum + 0x01, // Alignment + 0x20, // Length + ) + IRQNoFlags () + {6} + }) + } + Device (KBD) { Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID @@ -3246,26 +3263,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) } } - Scope (\_SB.PCI0.ISA) - { - Device (SMC) - { - Name (_HID, EisaId ("APP0001")) // _HID: Hardware ID - Name (_STA, 0x0B) // _STA: Status - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x0300, // Range Minimum - 0x0300, // Range Maximum - 0x01, // Alignment - 0x20, // Length - ) - IRQNoFlags () - {6} - }) - } - } - Scope (\_SB) { Scope (PCI0) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-26-imammedo@redhat.com>
2022-06-09acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide device's AMLIgor Mammedov3-36/+29
.. and clean up not longer needed conditionals in DSTD build code. applesmc AML will be fetched and included when ISA bridge will build its own AML code (incl. attached devices). Expected AML change: the device under separate _SB.PCI0.ISA scope is moved directly under Device(ISA) node. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-25-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: add applesmc testcaseIgor Mammedov1-0/+12
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-24-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: add and white-list DSDT.applesmc expected blobIgor Mammedov2-0/+1
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-23-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: update expected blobsIgor Mammedov33-32/+0
Expected AML change: ISA devices under separate _SB.PCI0.ISA scope are moved directly under Device(ISA) node. Example from PC machine, and q35 have similar changes: { Name (_ADR, 0x00010000) // _ADR: Address OperationRegion (P40C, PCI_Config, 0x60, 0x04) - } - } - - Scope (_SB.PCI0.ISA) - { - Device (KBD) - { - Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID - Name (_STA, 0x0F) // _STA: Status - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + Device (KBD) { - IO (Decode16, - 0x0060, // Range Minimum - 0x0060, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IO (Decode16, - 0x0064, // Range Minimum - 0x0064, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IRQNoFlags () - {1} - }) - } - - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID - Name (_STA, 0x0F) // _STA: Status - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IRQNoFlags () - {12} - }) - } + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x03F2, // Range Minimum - 0x03F2, // Range Maximum - 0x00, // Alignment - 0x04, // Length - ) - IO (Decode16, - 0x03F7, // Range Minimum - 0x03F7, // Range Maximum - 0x00, // Alignment - 0x01, // Length - ) - IRQNoFlags () - {6} - DMA (Compatibility, NotBusMaster, Transfer8, ) - {2} - }) - Device (FLPA) + Device (MOU) { - Name (_ADR, Zero) // _ADR: Address - Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { - Zero, - 0x05, - 0x4F, - 0x30, - One, - 0xAF, - 0x02, - 0x25, - 0x02, - 0x12, - 0x1B, - 0xFF, - 0x6C, - 0xF6, - 0x0F, - 0x08 + IRQNoFlags () + {12} }) } - Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + Device (FDC0) { - /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ - /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ - /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... - }) - } + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } - Device (LPT1) - { - Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID - Name (_UID, One) // _UID: Unique ID - Name (_STA, 0x0F) // _STA: Status - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) { - IO (Decode16, - 0x0378, // Range Minimum - 0x0378, // Range Maximum - 0x08, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {7} - }) - } + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } - Device (COM1) - { - Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID - Name (_UID, One) // _UID: Unique ID - Name (_STA, 0x0F) // _STA: Status - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + Device (COM1) { - IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x00, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {4} - }) - } + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + Device (RTC) { - IO (Decode16, - 0x0070, // Range Minimum - 0x0070, // Range Maximum - 0x01, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {8} - }) + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } } } Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220609115113.3478093-1-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: q35: isa bridge: use AcpiDevAmlIf interface to build ISA device ↵Igor Mammedov2-19/+30
descriptors replaces adhoc build_isa_devices_aml() with generic AcpiDevAmlIf way to build bridge AML including all devices that are attached to its ISA bus. Later when PCI is converted to AcpiDevAmlIf, build_q35_isa_bridge() will also be dropped since PCI parts itself will take care of building device prologue/epilogue AML for each enumerated PCI device. Expected AML change is contextual, where ISA devices are moved from separately declared _SB.PCI0.ISA scope, directly under Device(ISA) node. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-21-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: pc: isa bridge: use AcpiDevAmlIf interface to build ISA device descriptorsIgor Mammedov2-5/+28
replaces ad-hoc build_isa_devices_aml() with generic AcpiDevAmlIf way to build bridge AML including all devices that are attached to its ISA bus. Later when PCI is converted to AcpiDevAmlIf, build_piix4_isa_bridge() will also be dropped since PCI parts itself will take care of building device prologue/epilogue AML for each enumerated PCI device. Expected AML change is contextual, where ISA devices are moved from separately declared _SB.PCI0.ISA scope , directly under Device(ISA) node. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-20-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: white-list to be re-factored pc/q35 DSDTIgor Mammedov1-0/+32
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220609114855.3477822-1-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09q35: acpi: drop not needed PCMachineClass::do_not_add_smb_acpiIgor Mammedov4-4/+1
by default we do not version ACPI AML as it's considered a part of firmware. Drop do_not_add_smb_acpi that blocked SMBUS AML description on 3.1 and older machine types without providing justification. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-18-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device descriptorsIgor Mammedov7-47/+42
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices to a generic approach (i.e. make devices provide its own AML blobs like it is done with other ISA devices (ex. KBD)) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-17-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: ich9-smb: add support for AcpiDevAmlIf interfaceIgor Mammedov1-0/+15
wire AcpiDevAmlIf interface to build ich9-smb and its slave devices AML. It will be used by followup patches to switch from creating AML in ad-hoc way to a more systematic one that will scan present devices and ask them to provide their AML code like it's done with ISA devices. This patch is a partial conversion, as it only fetches AML from slave devices attached to its I2C bus. The conversion will be completed when PCI bus is switched to use AcpiDevAmlIf and build_smb0() could be dropped. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-16-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: update expected DSDT.ipmismbus blobIgor Mammedov2-1/+0
expected AML change: Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0, - AddressingMode7Bit, "\\_SB.PCI0.SMB0", + AddressingMode7Bit, "^", 0x00, ResourceProducer, , Exclusive, ) }) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-15-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09ipmi: acpi: use relative path to resource sourceIgor Mammedov4-10/+10
smbus-ipmi AML description needs to specify a path to its parent node in _CRS. The rest of IPMI inplementations (ISA based) do not need path at all. Instead of passing through a full path use relative path to point to smbus-ipmi's parent node, it will let follow up patches to create IPMI device AML in a generic way instead of current ad-hoc way. (i.e. AML will be generated the same way it's done for other ISA device, and smbus will be converted to generate AML for its slave devices the same way as ISA) expected AML change: Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0, - AddressingMode7Bit, "\\_SB.PCI0.SMB0", + AddressingMode7Bit, "^", 0x00, ResourceProducer, , Exclusive, ) }) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-14-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: whitelist DSDT.ipmismbus expected blobIgor Mammedov1-0/+1
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-13-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: update expected blob DSDT.ipmismbusIgor Mammedov2-1/+0
basic q35 DSDT with an extra device node: Device (MI1) { Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID Name (_STR, "ipmi_smbus") // _STR: Description String Name (_UID, One) // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0, AddressingMode7Bit, "\\_SB.PCI0.SMB0", 0x00, ResourceProducer, , Exclusive, ) }) Name (_IFT, 0x04) // _IFT: IPMI Interface Type Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision } Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-12-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: q35: add test for smbus-ipmi deviceIgor Mammedov1-0/+16
expected new device node: Device (MI1) { Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID Name (_STR, "ipmi_smbus") // _STR: Description String Name (_UID, One) // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBusV2 (0x0000, ControllerInitiated, 0x000186A0, AddressingMode7Bit, "\\_SB.PCI0.SMB0", 0x00, ResourceProducer, , Exclusive, ) }) Name (_IFT, 0x04) // _IFT: IPMI Interface Type Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision } Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-11-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09tests: acpi: add and whitelist DSDT.ipmismbus expected blobIgor Mammedov2-0/+1
.. which will be used by follow up smbus-ipmi test-case Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220608135340.3304695-10-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09isa-bus: drop no longer used ISADeviceClass::build_amlIgor Mammedov2-12/+1
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-9-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: pckbd: replace ISADeviceClass::build_aml with ↵Igor Mammedov1-5/+9
AcpiDevAmlIfClass:build_dev_aml Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-8-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: mc146818rtc: replace ISADeviceClass::build_aml with ↵Igor Mammedov1-5/+9
AcpiDevAmlIfClass:build_dev_aml Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-7-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: serial-is: replace ISADeviceClass::build_aml with ↵Igor Mammedov1-5/+9
AcpiDevAmlIfClass:build_dev_aml Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-6-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: parallel port: replace ISADeviceClass::build_aml with ↵Igor Mammedov1-5/+9
AcpiDevAmlIfClass:build_dev_aml Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-5-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: fdc-isa: replace ISADeviceClass::build_aml with ↵Igor Mammedov2-7/+10
AcpiDevAmlIfClass:build_dev_aml Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: make isa_build_aml() support AcpiDevAmlIf interfaceIgor Mammedov1-0/+5
To allow incremental conversion from ISADeviceClass::build_aml to AcpiDevAmlIf, add support for the later without removing the former. Once conversion is complete, another commit will drop ISADeviceClass::build_aml related code. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-09acpi: add interface to build device specific AMLIgor Mammedov3-1/+49
There is already ISADeviceClass::build_aml() callback which builds device specific AML blob for some ISA devices. To extend the same idea to other devices, add TYPE_ACPI_DEV_AML_IF Interface that will provide a more generic callback which will be used not only for ISA but other devices. It will allow get rid of some data-mining and ad-hoc AML building, by asking device(s) to generate its own AML blob like it's done for ISA devices. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20220608135340.3304695-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis1-11/+46
There are currently two types of RISC-V CPUs: - Generic CPUs (base or any) that allow complete custimisation - "Named" CPUs that match existing hardware Users can use the base CPUs to custimise the extensions that they want, for example -cpu rv64,v=true. We originally exposed these as part of the named CPUs as well, but that was by accident. Exposing the CPU properties to named CPUs means that we accidently enable extensions that don't exist on the CPUs by default. For example the SiFive E CPU currently support the zba extension, which is a bug. This patch instead only exposes the CPU extensions to the generic CPUs. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220608061437.314434-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail ↵eopXD1-0/+2
agnostic behavior According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between tail policies. Setting agnostic elements to all 1s allows QEMU to express this. This commit adds option 'rvv_ta_all_1s' is added to enable the behavior, it is default as disabled. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-16@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD2-2/+45
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-15@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD2-0/+36
The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-14@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD1-0/+20
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-13@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD2-196/+261
Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-12@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic ↵eopXD1-106/+114
instructions Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-11@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move ↵eopXD2-4/+28
instructions Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-10@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD1-0/+18
Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-9@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD2-1/+13
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-8@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD3-142/+190
`vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD3-0/+68
Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as tail elements. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-6@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD6-132/+178
According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between tail policies. Setting agnostic elements to all 1s allows QEMU to express this. This is the first commit regarding the optional tail agnostic behavior. Follow-up commits will add this optional behavior for all rvv instructions. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD1-0/+27
According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselves require vstart to be zero. So they don't need the early exit. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-4@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Rename ambiguous eszeopXD1-38/+38
No functional change intended in this commit. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-3@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Prune redundant access_type parameter passedeopXD1-19/+16
No functional change intended in this commit. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-2@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: rvv: Prune redundant ESZ, DSZ parameter passedeopXD1-567/+565
No functional change intended in this commit. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-1@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv/debug.c: keep experimental rv128 support workingFrédéric Pétrot1-0/+2
Add an MXL_RV128 case in two switches so that no error is triggered when using the -cpu x-rv128 option. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker3-2/+3
Whether or not VSEIP is pending isn't reflected in env->mip and must instead be determined from hstatus.vgein and hgeip. As a result a CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as specified in the privileged ISA. Just use riscv_cpu_all_pending() instead, which already accounts for VSEIP. Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220531210544.181322-1-abrestic@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10hw/core/loader: return image sizes as ssize_tJamie Iles7-75/+80
Various loader functions return an int which limits images to 2GB which is fine for things like a BIOS/kernel image, but if we want to be able to load memory images or large ramdisks then any file over 2GB would silently fail to load. Cc: Luc Michel <lmichel@kalray.eu> Signed-off-by: Jamie Iles <jamie@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Luc Michel <lmichel@kalray.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211111141141.3295094-2-jamie@nuviainc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10hw/intc: sifive_plic: Avoid overflowing the addr_config bufferAlistair Francis1-10/+9
Since commit ad40be27 "target/riscv: Support start kernel directly by KVM" we have been overflowing the addr_config on "M,MS..." configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050. This commit changes the loop in sifive_plic_create() from iterating over the number of harts to just iterating over the addr_config. The addr_config is based on the hart_config, and will contain interrup details for all harts. This way we can't iterate past the end of addr_config. Fixes: ad40be27084536 ("target/riscv: Support start kernel directly by KVM") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1050 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220601013631.196854-1-alistair.francis@opensource.wdc.com>
generated by cgit v1.1 at 2025-08-10 13:30:43 +0000