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2024-05-05target/sparc: Fix FMULD8*X16Richard Henderson3-52/+44
Not only do these instructions have f32 inputs, they also do not perform rounding. Since these are relatively simple, implement them properly inline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240502165528.244004-6-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05target/sparc: Fix FMUL8x16A{U,L}Richard Henderson3-40/+48
These instructions have f32 inputs, which changes the decode of the register numbers. While we're fixing things, use a common helper for both insns, extracting the 16-bit scalar in tcg beforehand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240502165528.244004-5-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05target/sparc: Fix FMUL8x16Richard Henderson3-6/+26
This instruction has f32 as source1, which alters the decoding of the register number, which means we've been passing the wrong data for odd register numbers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240502165528.244004-4-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05target/sparc: Fix FEXPANDRichard Henderson4-6/+24
This is a 2-operand instruction, not 3-operand. Worse, we took the source from the wrong operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240502165528.244004-3-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05linux-user/sparc: Add more hwcap bits for sparc64Richard Henderson1-14/+34
Supply HWCAP_SPARC_V8PLUS, HWCAP_SPARC_MUL32, HWCAP_SPARC_DIV32, HWCAP_SPARC_POPC, HWCAP_SPARC_FSMULD, HWCAP_SPARC_VIS, HWCAP_SPARC_VIS2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240502165528.244004-2-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05hw/sparc64: set iommu_platform=on for virtio devices attached to the sun4u ↵Mark Cave-Ayland1-0/+7
machine The sun4u machine has an IOMMU and therefore it is possible to program it such that the virtio-device IOVA does not map directly to the CPU physical address. This is not a problem with Linux which always maps the IOVA directly to the CPU physical address, however it is required for the NetBSD virtio driver where this is not the case. Set the sun4u machine defaults for all virtio devices so that disable-legacy=on and iommu_platform=on to ensure a default configuration will allow virtio devices to function correctly on both Linux and NetBSD. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20240418205730.31396-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05docs/about: Deprecate the old "UltraSparc" CPU names that contain a "+"Thomas Huth1-0/+9
For consistency we should drop the names with a "+" in it in the long run. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240419084812.504779-5-thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05docs/system/target-sparc: Improve the Sparc documentationThomas Huth1-5/+7
Add some words about how to enable or disable boolean features, and remove the note about a Linux kernel being available on the QEMU website (they have been removed long ago already), and the note about NetBSD and OpenBSD still having issues (they should work fine nowadays). Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2141 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240419084812.504779-4-thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05target/sparc/cpu: Avoid spaces by default in the CPU namesThomas Huth1-28/+28
The output of "-cpu help" is currently rather confusing to the users: It might not be fully clear which part of the output defines the CPU names since the CPU names contain white spaces (which we later have to convert into dashes internally). At best it's at least a nuisance since the users might need to specify the CPU names with quoting on the command line if they are not aware of the fact that the CPU names could be written with dashes instead. So let's finally clean up this mess by using dashes instead of white spaces for the CPU names, like we're doing it internally later (and like we're doing it in most other targets of QEMU). Note that it is still possible to pass the CPU names with spaces to the "-cpu" option, since sparc_cpu_type_name() still translates those to "-". Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2141 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240419084812.504779-3-thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-05target/sparc/cpu: Rename the CPU models with a "+" in their namesThomas Huth2-10/+12
Commit b447378e12 ("qom/object: Limit type names to alphanumerical ...") cut down the amount of allowed characters for QOM types to a saner set. The "+" character was meant to be included in this set, so we had to add a hack there to still allow the legacy names of POWER and Sparc64 CPUs. However, instead of putting such a hack in the common QOM code, there is a much better place to do this: The sparc_cpu_class_by_name() function which is used to look up the names of all Sparc CPUs. Thus let's finally get rid of the "+" in the Sparc CPU names, and provide backward compatibility for the old names via some simple checks in the sparc_cpu_class_by_name() function. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240419084812.504779-2-thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2024-05-04Merge tag 'pull-axp-20240504' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson3-66/+91
target/alpha: Implement CF_PCREL # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmY2VlYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/IxQf/UAxpxtc+glkuZ17C # mUliqx/Vif31BuKw31GVSDENOMteD900fR8+nNGY401+2hdZxoNo2N70ZL1h9AgX # xWVz1H33MwBXbW3lWhGSpikJ/Sd3K7dsqZpRWlr1uUEFmNXDSihKgY3JfhJ4mEsq # 8IIITyixSiiRyl1HBgfCUqLfHkWQamHz/Tbmku9wvOZ5fYkPHV1kCmlQ8X89iB9j # yxHW9Zcm8cShD0w4pU1HZAttHhyNZrB70ebauksAWX6QIG6fdTv+qMz9XP4FofuT # SwLuYja3ohoTijFkC7ctA0dbsF3xwCFKES6CdP8Ne5cKHSzsrejZhh8z/0uHi+D2 # jwxnMg== # =oK6Y # -----END PGP SIGNATURE----- # gpg: Signature made Sat 04 May 2024 08:37:58 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-axp-20240504' of https://gitlab.com/rth7680/qemu: target/alpha: Implement CF_PCREL target/alpha: Split out gen_pc_disp target/alpha: Split out gen_goto_tb target/alpha: Simplify gen_bcond_internal() target/alpha: Return DISAS_NORETURN once target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURN target/alpha: Use DISAS_NEXT definition instead of magic '0' value target/alpha: Hoist branch shift to initial decode target/alpha: Use cpu_env in preference to ALPHA_CPU Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-04target/alpha: Implement CF_PCRELRichard Henderson2-5/+47
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-10-philmd@linaro.org>
2024-05-04target/alpha: Split out gen_pc_dispRichard Henderson1-18/+23
Prepare for pcrel by not modifying cpu_pc before use, in the case of JSR. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-9-philmd@linaro.org>
2024-05-04target/alpha: Split out gen_goto_tbRichard Henderson1-37/+16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 5/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-8-philmd@linaro.org>
2024-05-04target/alpha: Simplify gen_bcond_internal()Philippe Mathieu-Daudé1-10/+9
Richard Henderson explained on IRC: bcond_internal() used to insist that both branch destination and branch fallthrough are use_goto_tb; if not, we'd use movcond to compute an indirect jump. But it's perfectly fine for e.g. the branch fallthrough to use_goto_tb, and the branch destination to use an indirect branch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 4/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-7-philmd@linaro.org>
2024-05-04target/alpha: Return DISAS_NORETURN onceRichard Henderson1-5/+4
Trivial change to make next commits easier to understand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 3/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-6-philmd@linaro.org>
2024-05-04target/alpha: Inline DISAS_PC_UPDATED and return DISAS_NORETURNRichard Henderson1-2/+4
Inline DISAS_PC_UPDATED switch case from alpha_tr_tb_stop(): switch (ctx->base.is_jmp) { ... case DISAS_PC_UPDATED: tcg_gen_lookup_and_goto_ptr(); break; Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 2/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-5-philmd@linaro.org>
2024-05-04target/alpha: Use DISAS_NEXT definition instead of magic '0' valueRichard Henderson1-2/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240424234436.995410-4-richard.henderson@linaro.org> [PMD: Split bigger patch, part 1/5] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-4-philmd@linaro.org>
2024-05-04target/alpha: Hoist branch shift to initial decodeRichard Henderson1-3/+3
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-3-philmd@linaro.org>
2024-05-04target/alpha: Use cpu_env in preference to ALPHA_CPURichard Henderson2-13/+10
ALPHA_CPU has a dynamic object type assert, which is unnecessary considering that these are all class hooks. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240503072014.24751-2-philmd@linaro.org>
2024-05-03Merge tag 'accel-sh4-ui-20240503' of https://github.com/philmd/qemu into stagingRichard Henderson20-46/+112
- Fix NULL dereference in NVMM & WHPX init_vcpu() - Move user emulation headers "exec/user" to "user" - Fix SH-4 ADDV / SUBV opcodes - Drop Cocoa compatility on macOS <= 10.12 - Update Anthony PERARD email # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmY1BE4ACgkQ4+MsLN6t # wN73jg//dbdHQU+4oM7BgTduDZn1ulKz5DtNEJawRP6vxIcSQ+Co2Yd+gdLOSXNI # 2BaoiOQ8cyDEHj1Uud3WVB0GsQYvHrqgXcjeHpX6yFFCZNyRvzEXizJPHKCtq+4e # XQFtfTFftlJdaKCLqyDqVnrVNRacFPm7kinrEQbTSmglAhwnyu3GwsokDAYiJTqp # g0n6mX/pWVEMDNY1HrDsk2Q/pyIZFmzhtuRyXRvi/bh8/BnmMCpySG+2463dnu1O # xIGr2w8ldc+mKn2w2k3wYKDnUHz/NhOkE86tL/ZxIgjCzeenZXwXNdzM+cuAmOZX # L9KIu5io6bTevYVwwHhd5/N6MCqVEhoRmsUQfF0CIkIzxXbyF14M89YHXZo3YJAd # n2uoJ7i6hF/4Pt6Uqlg09+vEk7onwrobnTPnbKHEKNWHNOMKXpq1CBxxcVz2qe24 # +CTAAOOhHqaTjODPSexzHZDZYxugCy1XSqps9AFF1HqUcmsPCL/PQ75YGTJJO0oF # 0V1Yvzjhin26AQS9SglIeXnHxYC26Cg2mXnUpVbryWnG888r0XAGpRl+FEuXK7Ln # /dGuCIWTozypSkG9304IlxlYsOoXhL11NZqINW+W/Tor3dMRQhWUQcHqv98Jl4Ad # rnpzZ0Dhd9ityZdbI0CCMZZZLY5dw1Rq5q407GTJr1CDU4PJBh0= # =N8q0 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 May 2024 08:35:42 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'accel-sh4-ui-20240503' of https://github.com/philmd/qemu: ui/cocoa.m: Drop old macOS-10.12-and-earlier compat ifdefs target/sh4: Rename TCGv variables as manual for SUBV opcode target/sh4: Rename TCGv variables as manual for ADDV opcode target/sh4: Fix SUBV opcode target/sh4: Fix ADDV opcode MAINTAINERS: Update my email address plugins: Update stale comment plugins/api: Only include 'exec/ram_addr.h' with system emulation coverity: Update user emulation regexp user: Move 'thunk.h' from 'exec/user' to 'user' user: Move 'abitypes.h' from 'exec/user' to 'user' exec: Include missing license in 'exec/cpu-common.h' accel/whpx: Fix NULL dereference in whpx_init_vcpu() accel/nvmm: Fix NULL dereference in nvmm_init_vcpu() Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03ui/cocoa.m: Drop old macOS-10.12-and-earlier compat ifdefsPeter Maydell1-13/+0
We only support the most recent two versions of macOS (currently macOS 13 Ventura and macOS 14 Sonoma), and our ui/cocoa.m code already assumes at least macOS 12 Monterey or better, because it uses NSScreen safeAreaInsets, which is 12.0-or-newer. Remove the ifdefs that were providing backwards compatibility for building on 10.12 and earlier versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240502142904.62644-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03target/sh4: Rename TCGv variables as manual for SUBV opcodePhilippe Mathieu-Daudé1-6/+10
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how underflow is calculated. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240430163125.77430-5-philmd@linaro.org>
2024-05-03target/sh4: Rename TCGv variables as manual for ADDV opcodePhilippe Mathieu-Daudé1-6/+10
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how overflow is calculated. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-4-philmd@linaro.org>
2024-05-03target/sh4: Fix SUBV opcodePhilippe Mathieu-Daudé3-1/+34
The documentation says: SUBV Rm, Rn Rn - Rm -> Rn, underflow -> T The overflow / underflow can be calculated as: T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 However we were using the incorrect: T = ((Rn ^ Rm) & (Result ^ Rm)) >> 31 Fix by using the Rn register instead of Rm. Add tests provided by Paul Cercueil. Cc: qemu-stable@nongnu.org Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <paul@crapouillou.net> Suggested-by: Paul Cercueil <paul@crapouillou.net> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2318 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-3-philmd@linaro.org>
2024-05-03target/sh4: Fix ADDV opcodePhilippe Mathieu-Daudé3-1/+31
The documentation says: ADDV Rm, Rn Rn + Rm -> Rn, overflow -> T But QEMU implementation was: ADDV Rm, Rn Rn + Rm -> Rm, overflow -> T Fix by filling the correct Rm register. Add tests provided by Paul Cercueil. Cc: qemu-stable@nongnu.org Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <paul@crapouillou.net> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <20240430163125.77430-2-philmd@linaro.org>
2024-05-03MAINTAINERS: Update my email addressAnthony PERARD1-1/+1
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Paul Durrant <paul@xen.org> Acked-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240429154938.19340-1-anthony.perard@citrix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03plugins: Update stale commentPhilippe Mathieu-Daudé1-1/+1
"plugin_mask" was renamed as "event_mask" in commit c006147122 ("plugins: create CPUPluginState and migrate plugin_mask"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-05-03plugins/api: Only include 'exec/ram_addr.h' with system emulationPhilippe Mathieu-Daudé1-1/+1
"exec/ram_addr.h" shouldn't be used with user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-4-philmd@linaro.org>
2024-05-03coverity: Update user emulation regexpPhilippe Mathieu-Daudé1-1/+1
All user emulation headers are now under include/user/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-3-philmd@linaro.org>
2024-05-03user: Move 'thunk.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé5-6/+9
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-2-philmd@linaro.org>
2024-05-03user: Move 'abitypes.h' from 'exec/user' to 'user'Philippe Mathieu-Daudé6-7/+7
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240503125202.35667-1-philmd@linaro.org>
2024-05-03exec: Include missing license in 'exec/cpu-common.h'Philippe Mathieu-Daudé1-2/+7
Commit 1ad2134f91 ("Hardware convenience library") extracted "cpu-common.h" from "cpu-all.h", which uses the LGPL-2.1+ license. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-5-philmd@linaro.org>
2024-05-03Merge tag 'pull-misc-20240503' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson4-210/+313
util/bufferiszero: - Remove sse4.1 and avx512 variants - Reorganize for early test for acceleration - Remove useless prefetches - Optimize sse2, avx2 and integer variants - Add simd acceleration for aarch64 - Add bufferiszero-bench # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmY0/qMdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+ULQf/T2JSdvG6/EjDCf4N # cnSGiUV2MIeByw8tkrc/fWCNdlulHhk9gbg9l+f2muwK8H/k2BdynbrQnt1Ymmtk # xzM6+PNOcByaovSAkvNweZVbrQX36Yih9S7f3n+xcxfVuvvYhKSLHXLkeqO96LMd # rN+WRpxhReaU3n8/FO7o3S26SRpk7X9kRfShaT7U7ytHGjGsXUvMKIRs30hbsJTB # yjed0a0u54FoSlN6AEqjWdgzaWP8nT65+8Yxe3dzB9hx09UiolZo60eHqYy7Mkno # N6aMOB6gUUbCiKZ3Qk+1zEX97vl26NH3zt5tIIJTWDoIkC3f9qbg1x5hwWLQ3rra # rM8h8w== # =DnZO # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 May 2024 08:11:31 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-misc-20240503' of https://gitlab.com/rth7680/qemu: tests/bench: Add bufferiszero-bench util/bufferiszero: Add simd acceleration for aarch64 util/bufferiszero: Simplify test_buffer_is_zero_next_accel util/bufferiszero: Introduce biz_accel_fn typedef util/bufferiszero: Improve scalar variant util/bufferiszero: Optimize SSE2 and AVX2 variants util/bufferiszero: Remove useless prefetches util/bufferiszero: Reorganize for early test for acceleration util/bufferiszero: Remove AVX512 variant util/bufferiszero: Remove SSE4.1 variant Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03tests/bench: Add bufferiszero-benchRichard Henderson2-0/+48
Benchmark each acceleration function vs an aligned buffer of zeros. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Add simd acceleration for aarch64Richard Henderson1-0/+67
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely double-check with the compiler flags for __ARM_NEON and don't bother with a runtime check. Otherwise, model the loop after the x86 SSE2 function. Use UMAXV for the vector reduction. This is 3 cycles on cortex-a76 and 2 cycles on neoverse-n1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Simplify test_buffer_is_zero_next_accelRichard Henderson1-46/+35
Because the three alternatives are monotonic, we don't need to keep a couple of bitmasks, just identify the strongest alternative at startup. Generalize test_buffer_is_zero_next_accel and init_accel by always defining an accel_table array. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Introduce biz_accel_fn typedefRichard Henderson1-3/+4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Improve scalar variantRichard Henderson1-34/+51
Split less-than and greater-than 256 cases. Use unaligned accesses for head and tail. Avoid using out-of-bounds pointers in loop boundary conditions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Optimize SSE2 and AVX2 variantsAlexander Monakov1-41/+76
Increase unroll factor in SIMD loops from 4x to 8x in order to move their bottlenecks from ALU port contention to load issue rate (two loads per cycle on popular x86 implementations). Avoid using out-of-bounds pointers in loop boundary conditions. Follow SSE2 implementation strategy in the AVX2 variant. Avoid use of PTEST, which is not profitable there (like in the removed SSE4 variant). Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-6-amonakov@ispras.ru>
2024-05-03util/bufferiszero: Remove useless prefetchesAlexander Monakov1-3/+0
Use of prefetching in bufferiszero.c is quite questionable: - prefetches are issued just a few CPU cycles before the corresponding line would be hit by demand loads; - they are done for simple access patterns, i.e. where hardware prefetchers can perform better; - they compete for load ports in loops that should be limited by load port throughput rather than ALU throughput. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-5-amonakov@ispras.ru>
2024-05-03util/bufferiszero: Reorganize for early test for accelerationAlexander Monakov2-52/+62
Test for length >= 256 inline, where is is often a constant. Before calling into the accelerated routine, sample three bytes from the buffer, which handles most non-zero buffers. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Message-Id: <20240206204809.9859-3-amonakov@ispras.ru> [rth: Use __builtin_constant_p; move the indirect call out of line.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Remove AVX512 variantAlexander Monakov1-35/+3
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD routines are invoked much more rarely in normal use when most buffers are non-zero. This makes use of AVX512 unprofitable, as it incurs extra frequency and voltage transition periods during which the CPU operates at reduced performance, as described in https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-4-amonakov@ispras.ru> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-03util/bufferiszero: Remove SSE4.1 variantAlexander Monakov1-29/+0
The SSE4.1 variant is virtually identical to the SSE2 variant, except for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing if an SSE register is all zeroes. The PTEST instruction decodes to two uops, so it can be handled only by the complex decoder, and since CMP+JNE are macro-fused, both sequences decode to three uops. The uops comprising the PTEST instruction dispatch to p0 and p5 on Intel CPUs, so PCMPEQB+PMOVMSKB is comparatively more flexible from dispatch standpoint. Hence, the use of PTEST brings no benefit from throughput standpoint. Its latency is not important, since it feeds only a conditional jump, which terminates the dependency chain. I never observed PTEST variants to be faster on real hardware. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Mikhail Romanov <mmromanov@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240206204809.9859-2-amonakov@ispras.ru>
2024-05-03accel/whpx: Fix NULL dereference in whpx_init_vcpu()Philippe Mathieu-Daudé1-1/+1
When mechanically moving the @dirty field to AccelCPUState in commit 9ad49538c7, we neglected cpu->accel is still NULL when we want to dereference it. Fixes: 9ad49538c7 ("accel/whpx: Use accel-specific per-vcpu @dirty field") Reported-by: Volker Rümelin <vr_qemu@t-online.de> Suggested-by: Volker Rümelin <vr_qemu@t-online.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429091918.27429-2-philmd@linaro.org>
2024-05-03accel/nvmm: Fix NULL dereference in nvmm_init_vcpu()Philippe Mathieu-Daudé1-1/+1
When mechanically moving the @dirty field to AccelCPUState in commit 79f1926b2d, we neglected cpu->accel is still NULL when we want to dereference it. Reported-by: Volker Rümelin <vr_qemu@t-online.de> Suggested-by: Volker Rümelin <vr_qemu@t-online.de> Fixes: 79f1926b2d ("accel/nvmm: Use accel-specific per-vcpu @dirty field") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240429091918.27429-3-philmd@linaro.org>
2024-05-01Merge tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson19-930/+391
plugins: Rewrite plugin tcg expansion # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmYyUpkdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV98VAgAoTqIWPHtPJOS800G # TlFuQjkEzQCPSKAh6ZbotsAMvfNwBloPpdrUlFr/jT7mURjEl2B7UC/4LzdhuGeQ # U/xZt5rXsYvyfS3VwLf8pKBIscF7XjJ1rdfYMvBg9XaNp5VV0aEIk3+6P0uYtzXG # cREF0uCYfdK6uoiuifhqRAkgrNnamdwpPbbfvzDQI13wICW7SfR7dcd629clVZ1O # QvD1M4bpTWyhClbZzaoHqyPs+HQEM/AY0wOTfYZNbQBu6zFZXNDZCvYhIEWonPBO # AKe5KWUrQMwLJhRVejaSSZZDjMdcz3HLaGJppP89/WB+gpY09+LsiuqT7k5c12Bw # ueLEhw== # =mn63 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 May 2024 07:32:57 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20240501' of https://gitlab.com/rth7680/qemu: plugins: Update the documentation block for plugin-gen.c plugins: Inline plugin_gen_empty_callback plugins: Merge qemu_plugin_tb_insn_get to plugin-gen.c plugins: Split out common cb expanders plugins: Replace pr_ops with a proper debug dump flag plugins: Introduce PLUGIN_CB_MEM_REGULAR plugins: Simplify callback queues tcg: Remove INDEX_op_plugin_cb_{start,end} tcg: Remove TCG_CALL_PLUGIN plugins: Remove plugin helpers plugins: Use emit_before_op for PLUGIN_GEN_FROM_MEM plugins: Use emit_before_op for PLUGIN_GEN_FROM_INSN plugins: Add PLUGIN_GEN_AFTER_TB plugins: Use emit_before_op for PLUGIN_GEN_FROM_TB plugins: Use emit_before_op for PLUGIN_GEN_AFTER_INSN plugins: Create TCGHelperInfo for all out-of-line callbacks plugins: Move function pointer in qemu_plugin_dyn_cb plugins: Zero new qemu_plugin_dyn_cb entries tcg: Pass function pointer to tcg_gen_call* tcg: Make tcg/helper-info.h self-contained Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-01Merge tag 'pull-ufs-20240429' of https://gitlab.com/jeuk20.kim/qemu into stagingRichard Henderson1-0/+8
ufs queue # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEUBfYMVl8eKPZB+73EuIgTA5dtgIFAmYvEScACgkQEuIgTA5d # tgL3Qg//R3IcISQqqDaJ/ySzKGmkyohJSc6ySLYvla4Aki7PV+um2Dx/XNS7uG2b # d3Qz4m6QaOKsocLfldRTn2FxVK238Rp5HNny5vc0kGRdwpR514B7aU0FhpT7qObS # wbbgRdDddIBIiCFLhtXtg5/TK2h32VxGrVI6llX4gmd2VzqM0e4xeG1Oj8rZseOY # SAgvDv68s1YwlO1p1vPvst/H+mUKYkqtPN1mjfCIn5tM6ss8kCLUnKjqGAg1BnSN # xwaGrqqOlzQK2+aV02eiItiow8evU/h+c9eiTnBo/EvBwjoBn6flNXABWXFENnmP # JjVIFeiNzSFhBPDzO23GXviuEt96j5lrcGYR48HYMZfEbJNpblXzWvEGMZWnXNgx # Q3cpcarZ4vSWIflR9OnCSQaGLA0Ny6YqLbmrM/oD+v67EITafKKc+flmiF7DBASB # fUoEsdffdA37LDtygJb7hfUhvPQWWAujmGzZ1cDP8Oa0MhT7aiD0Z/WqhhjVQbM0 # iLiCDDD0cc0pmT3vw3EnEjKjnSkY3H62Q7pnYHiQgij4Ls/Rdd/P7OkSd0aI82t0 # TooWGZJnyf8rjAzY2cEB1Twrhmhuyt9NnGxip9W8JsQBZMLabD2CahOm83zsk7jZ # 3fOONz6XrW2ttFkLZcRd4x4YjKONjEXsSX2ZrXTZ5t3USz/VNvY= # =Vwyi # -----END PGP SIGNATURE----- # gpg: Signature made Sun 28 Apr 2024 08:16:55 PM PDT # gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602 # gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown] # gpg: aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602 * tag 'pull-ufs-20240429' of https://gitlab.com/jeuk20.kim/qemu: hw/ufs: Fix buffer overflow bug Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-01Merge tag 'qga-pull-2024-05-01' of https://github.com/kostyanf14/qemu into ↵Richard Henderson9-283/+999
staging qga-pull-2024-05-01 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEwsLBCepDxjwUI+uE711egWG6hOcFAmYx8fgACgkQ711egWG6 # hOflAw//fDHAQzcrWFggn4Ly1p1QQK+AYdQPbmKCIV7j64k05kCFU+bQxbMT9Fmr # RsWPXHv5t36ySKxaML412r7fqX19bm7RP31hlau76KtZsTJXFR/dbC6jNWXi/Qfd # 5Z1mwK4lyW+TROPx6gA2tZddqAZsSxLlArhXGj9nUcQBXDebKD/rO4jYrRBWI7uG # hV2mmolGbsNSzinfhujY2yVpm3SMEEc9IQ/CDd11HUsgJjAkXVxCDfKDXCmMKUAm # 7B6VYjQpy6zjXG/eWxIp2b7HVyEEAazHizk431IwDPXpf4G8kecEVTEdQrh6tea1 # ojlfv4KhA5TuKSrhUKO+hGWeXbHfORhxryjagbwGnTd15Dq7B8SEMcubuNXJJiLJ # G9kuqvAOrZcE/TQbdAr5Zv2vpg0Hh0ZsOrFCn+THES31oD5mgeLTwmXcguPwEyBV # BT2Pd1UwOXumS+L065Am7PRm+i80C1J3e1dcN9+puBdNkp/kwR9RLMxDpKwEEVtI # CMpiay4K5evFvXPAl6zFLKOYaeUiEKsxSwfj6A4ZgkuKWPb0TpIqY3vdw6TwvXI+ # lk136hcOxQ6SKJOw11wESOsWgTbqOzgevNsLlQIm3l7MSGJcQOKJwWIU7VFp4qbp # kJnMeHtlXkkpppXMMKZsa0hXWWXM+miQNSFQhdCEW7KWAWNU5dk= # =Q49V # -----END PGP SIGNATURE----- # gpg: Signature made Wed 01 May 2024 12:40:40 AM PDT # gpg: using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7 # gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign) <kkostiuk@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7 * tag 'qga-pull-2024-05-01' of https://github.com/kostyanf14/qemu: qga: Implement SSH commands for Windows qga: Refactor common SSH functions qga/commands-posix: qmp_guest_set_user_password: use ga_run_command helper qga/commands-posix: don't do fork()/exec() when suspending via sysfs qga/commands-posix: execute_fsfreeze_hook: use ga_run_command helper qga/commands-posix: qmp_guest_set_time: use ga_run_command helper qga/commands-posix: qmp_guest_shutdown: use ga_run_command helper qga: introduce ga_run_command() helper for guest cmd execution qga: guest-get-fsinfo: add optional 'total-bytes-privileged' field Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-01qga: Implement SSH commands for Windowsaidaleuc4-11/+749
Signed-off-by: Aidan Leuck <aidan_leuck@selinc.com> Tested-by: Dehan Meng <demeng@redhat.com> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Link: https://lore.kernel.org/r/20240424144029.30665-3-aidan_leuck@selinc.com Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
generated by cgit v1.1 at 2025-01-15 22:04:44 +0000