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2013-12-20Add VSX Vector Move InstructionsTom Musta1-0/+71
This patch adds the vector move instructions: - xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision - xvabssp - Vector Absolute Value Single-Precision - xvnabssp - Vector Negative Absolute Value Single-Precision - xvnegsp - Vector Negate Single-Precision - xvcpsgnsp - Vector Copy Sign Single-Precision V3: Per Paolo Bonzini's suggestion, used a temporary for the sign mask and andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Scalar Move InstructionsTom Musta1-0/+70
This patch adds the VSX scalar move instructions: - xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision) A common generator macro (VSX_SCALAR_MOVE) is added since these instructions vary only slightly from each other. Macros to support VSX XX2 and XX3 form opcodes are also added. These macros handle the overloading of "opcode 2" space (instruction bits 26:30) caused by AX and BX bits (29 and 30, respectively). V3: Per feedback from Paolo Bonzini, moved the sign mask into a temporary and used andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20roms: Flush icache when writing roms to guest memoryAlexander Graf3-5/+47
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: tie spapr-nvram to -pflashPaolo Bonzini1-11/+3
spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20PPC: Use default pci bus name for grackle and heathrowAlexander Graf2-3/+3
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: add ibm, (get|set)-system-parameterAlexey Kardashevskiy2-0/+49
This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: replace return code constants with macrosAlexey Kardashevskiy7-67/+74
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: move POWER7+ to a separate familyAlexey Kardashevskiy3-1/+41
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvw4xTom Musta1-0/+28
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxsdxTom Musta1-0/+15
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvw4xTom Musta1-0/+29
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x) instruction. V2: changed to use deposit_i64 per Richard Henderson's review. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvdsxTom Musta1-0/+16
This patch adds the Load VSX Vector Doubleword & Splat Indexed (lxvdsx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxsdxTom Musta1-0/+16
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) instruction. The lower 8 bytes of the target register are undefined; this implementation leaves those bytes unaltered. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxpermdiTom Musta1-1/+40
This patch adds the xxpermdi instruction. The instruction uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX and BX). This results in overloading of the opcode table with aliases, which can be seen in the GEN_XX3FORM_DM macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvd2xTom Musta1-0/+18
This patch adds the stxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvd2xTom Musta1-0/+18
This patch adds the lxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSR to Global RegistersTom Musta1-0/+27
This patch adds VSX VSRs to the the list of global register indices. More specifically, it adds the lower halves of the first 32 VSRs to the list of global register indices. The upper halves of the first 32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs are already defined via the cpu_avrh[] and cpu_avrl[] arrays. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Instruction DecodersTom Musta1-0/+11
This patch adds decoders for the VSX fields XT, XS, XA, XB and DM. The first four are split fields and a general helper for these types of fields is also added. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add MSR VSX and Associated ExceptionTom Musta4-2/+18
This patch adds support for the VSX bit of the PowerPC Machine State Register (MSR) as well as the corresponding VSX Unavailable exception. The VSX bit is added to the defined bits masks of the Power7 and Power8 CPU models. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Declare and Enable VSXTom Musta2-3/+8
This patch adds the flag POWERPC_FLAG_VSX to the list of defined flags and also adds this flag to the list of supported features of the Power7 and Power8 CPUs. Additionally, the VSX instructions are added to the list of TCG-enabled instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy5-0/+56
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and a CPU version in lower 16 bits. Since there is no significant change in behavior between versions, there is no point to add every single CPU version in QEMU's CPU list. Also, new CPU versions of already supported CPU won't break the existing code. This adds PVR value/mask support for KVM, i.e. for -cpu host option. As CPU family class name for POWER7 is "POWER7-family", there is no need to touch aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: add stubs for KVM breakpointsGreg Kurz1-0/+28
The latest update to v3.13-rc3 (bf63839f) breaks the ppc build with KVM: kvm-all.o: In function `kvm_update_guest_debug': kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug' kvm-all.o: In function `kvm_insert_breakpoint': kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint' kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint' kvm-all.o: In function `kvm_remove_breakpoint': kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint' kvm-all.o: In function `kvm_remove_all_breakpoints': kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint' kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints' We need stubs until something gets implemented. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-19Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into ↵Anthony Liguori50-694/+5229
staging target-arm queue: * AES instruction support for 32 bit ARM * pflash01: much better emulation of 2x16bit and similar configs where multiple flash devices are banked together * fixed CBAR handling on Zynq, Highbank * initial AArch64 KVM control support * first two chunks of patches for A64 instruction emulation * new board: canon-a1100 (Canon DIGIC SoC) * new board: cubieboard (Allwinner A10 SoC) # gpg: Signature made Tue 17 Dec 2013 12:18:39 PM PST using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Alexander Graf (14) and others # Via Peter Maydell * pmaydell/tags/pull-target-arm-20131217: (62 commits) MAINTAINERS: add myself to maintain allwinner-a10 hw/arm: add cubieboard support hw/arm: add allwinner a10 SoC support hw/intc: add allwinner A10 interrupt controller hw/timer: add allwinner a10 timer vmstate: Add support for an array of ptimer_state * MAINTAINERS: Document 'Canon DIGIC' machine hw/arm/digic: add NOR ROM support hw/arm/digic: add UART support hw/arm/digic: add timer support hw/arm/digic: prepare DIGIC-based boards support hw/arm: add very initial support for Canon DIGIC SoC target-arm: A64: add support for logical (immediate) insns target-arm: A64: add support for 1-src CLS insn host-utils: add clrsb32/64 - count leading redundant sign bits target-arm: A64: add support for bitfield insns target-arm: A64: add support for 1-src REV insns target-arm: A64: add support for 1-src RBIT insn target-arm: A64: add support for 1-src data processing and CLZ target-arm: A64: add support for 2-src shift reg insns ... Message-id: 1387312160-12318-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-17MAINTAINERS: add myself to maintain allwinner-a10liguang1-0/+7
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Message-id: 1387159292-10436-7-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm: add cubieboard supportliguang3-1/+71
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-6-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm: add allwinner a10 SoC supportliguang4-0/+140
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/intc: add allwinner A10 interrupt controllerliguang4-0/+242
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/timer: add allwinner a10 timerliguang4-0/+316
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17vmstate: Add support for an array of ptimer_state *Peter Maydell2-0/+14
Add support for defining a vmstate field which is an array of pointers to structures, and use this to define a VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state* to be used by devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-2-git-send-email-lig.fnst@cn.fujitsu.com
2013-12-17MAINTAINERS: Document 'Canon DIGIC' machineAntony Pavlov1-0/+6
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-7-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add NOR ROM supportAntony Pavlov1-0/+78
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmail.com [PMM: don't try to load ROM blob if qtest_enabled()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add UART supportAntony Pavlov5-0/+261
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-5-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add timer supportAntony Pavlov5-0/+244
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-4-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: prepare DIGIC-based boards supportAntony Pavlov3-0/+86
Also this patch adds initial support for Canon PowerShot A1100 IS compact camera. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm: add very initial support for Canon DIGIC SoCAntony Pavlov4-0/+108
DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: A64: add support for logical (immediate) insnsAlexander Graf1-2/+173
This patch adds support for C3.4.4 Logical (immediate), which include AND, ANDS, ORR, EOR. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, function renaming, removed a TCG temp variable] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: cleaned up some unnecessary code in logic_imm_decode_wmask and added clarifying commentary on what it's actually doing. Dropped an ext32u that's not needed if we've just done an AND.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src CLS insnClaudio Fontana3-1/+31
this patch adds support for the CLS instruction. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17host-utils: add clrsb32/64 - count leading redundant sign bitsClaudio Fontana1-0/+32
this patch introduces wrappers for the clrsb builtins, which count the leading redundant sign bits. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for bitfield insnsClaudio Fontana1-2/+54
This patch implements the C3.4.2 Bitfield instructions: SBFM, BFM, UBFM. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src REV insnsClaudio Fontana1-1/+72
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src RBIT insnAlexander Graf3-0/+39
This adds support for the C5.6.147 RBIT instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, splitting REV into a separate patch] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana3-2/+56
This patch adds support for decoding 1-src data processing insns, and the first user, C5.6.40 CLZ (count leading zeroes). Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 2-src shift reg insnsAlexander Graf1-0/+22
This adds 2-src variable shift register instructions: C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use enums for shift types] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 2-src data processing and DIVAlexander Graf3-2/+93
This patch adds support for decoding 2-src data processing insns, and the first users, UDIV and SDIV. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder adding the 2-src decoding level, always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for EXTRAlexander Graf1-2/+47
This patch adds emulation support for the EXTR instruction. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more unallocated cases] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for ADR and ADRPAlexander Graf1-2/+23
Add support for the instructions described in "C3.4.6 PC-rel. addressing" (ADR and ADRP). Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: A64: add support for logical (shifted register)Alexander Graf1-6/+191
Add support for the instructions described in "C3.5.10 Logical (shifted register)". We store the flags in the same locations as the 32 bit decoder. This is slightly awkward when calculating 64 bit results, but seems a better tradeoff than having to rework the whole 32 bit decoder and also make 32 bit result calculation in A64 awkward. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: some refactoring to avoid hidden allocation of temps, rework flags, use enums for shift types, renaming of functions] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for conditional selectClaudio Fontana1-2/+65
This patch adds support for the instruction group "C3.5.6 Conditional select": CSEL, CSINC, CSINV, CSNEG. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: Improved code generated in the nomatch case as per RTH suggestions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for compare and branch immAlexander Graf1-2/+44
This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2013-12-17target-arm: A64: add support for 'test and branch' immAlexander Graf1-2/+25
This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.1 at 2025-02-11 07:11:13 +0000