| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-10-27 | vl: Allow ThreadContext objects to be created before the sandbox option | David Hildenbrand | 1 | -4/+32 |
| 2022-10-27 | hostmem: Allow for specifying a ThreadContext for preallocation | David Hildenbrand | 3 | -3/+15 |
| 2022-10-27 | util: Make qemu_prealloc_mem() optionally consume a ThreadContext | David Hildenbrand | 5 | -11/+22 |
| 2022-10-27 | util: Add write-only "node-affinity" property for ThreadContext | David Hildenbrand | 3 | -2/+93 |
| 2022-10-27 | util: Introduce ThreadContext user-creatable object | David Hildenbrand | 5 | -0/+354 |
| 2022-10-27 | util: Introduce qemu_thread_set_affinity() and qemu_thread_get_affinity() | David Hildenbrand | 4 | -0/+102 |
| 2022-10-27 | util: Cleanup and rename os_mem_prealloc() | David Hildenbrand | 6 | -23/+36 |
| 2022-10-24 | hw/mem/nvdimm: fix error message for 'unarmed' flag | Julia Suvorova | 1 | -1/+1 |
| 2022-10-20 | Merge tag 'pull-target-arm-20221020' of https://git.linaro.org/people/pmaydel... | Stefan Hajnoczi | 20 | -603/+914 |
| 2022-10-20 | hw/ide/microdrive: Use device_cold_reset() for self-resets | Peter Maydell | 1 | -4/+4 |
| 2022-10-20 | target/arm: Enable TARGET_TB_PCREL | Richard Henderson | 6 | -71/+178 |
| 2022-10-20 | target/arm: Introduce gen_pc_plus_diff for aarch32 | Richard Henderson | 1 | -17/+21 |
| 2022-10-20 | target/arm: Introduce gen_pc_plus_diff for aarch64 | Richard Henderson | 1 | -12/+29 |
| 2022-10-20 | target/arm: Change gen_jmp* to work on displacements | Richard Henderson | 1 | -16/+21 |
| 2022-10-20 | target/arm: Remove gen_exception_internal_insn pc argument | Richard Henderson | 2 | -8/+8 |
| 2022-10-20 | target/arm: Change gen_exception_insn* to work on displacements | Richard Henderson | 6 | -46/+43 |
| 2022-10-20 | target/arm: Change gen_*set_pc_im to gen_*update_pc | Richard Henderson | 5 | -54/+56 |
| 2022-10-20 | target/arm: Change gen_goto_tb to work on displacements | Richard Henderson | 2 | -23/+27 |
| 2022-10-20 | target/arm: Introduce curr_insn_len | Richard Henderson | 3 | -4/+8 |
| 2022-10-20 | target/arm: Use bool consistently for get_phys_addr subroutines | Richard Henderson | 1 | -4/+3 |
| 2022-10-20 | target/arm: Split out get_phys_addr_twostage | Richard Henderson | 1 | -91/+100 |
| 2022-10-20 | target/arm: Use softmmu tlbs for page table walking | Richard Henderson | 3 | -75/+145 |
| 2022-10-20 | target/arm: Move be test for regime into S1TranslateResult | Richard Henderson | 1 | -2/+4 |
| 2022-10-20 | target/arm: Plumb debug into S1Translate | Richard Henderson | 1 | -18/+37 |
| 2022-10-20 | target/arm: Split out S1Translate type | Richard Henderson | 1 | -61/+79 |
| 2022-10-20 | target/arm: Restrict tlb flush from vttbr_write to vmid change | Richard Henderson | 1 | -2/+2 |
| 2022-10-20 | target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx | Richard Henderson | 3 | -49/+127 |
| 2022-10-20 | target/arm: Add ARMMMUIdx_Phys_{S,NS} | Richard Henderson | 3 | -4/+24 |
| 2022-10-20 | target/arm: Use probe_access_full for BTI | Richard Henderson | 5 | -31/+20 |
| 2022-10-20 | target/arm: Use probe_access_full for MTE | Richard Henderson | 5 | -86/+36 |
| 2022-10-20 | target/arm: Enable TARGET_PAGE_ENTRY_EXTRA | Richard Henderson | 2 | -0/+15 |
| 2022-10-20 | target/arm: update the cortex-a15 MIDR to latest rev | Alex Bennée | 1 | -1/+3 |
| 2022-10-20 | hw/char/pl011: fix baud rate calculation | Baruch Siach | 1 | -1/+1 |
| 2022-10-18 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Stefan Hajnoczi | 32 | -2931/+5980 |
| 2022-10-18 | Merge tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu into staging | Stefan Hajnoczi | 37 | -370/+589 |
| 2022-10-18 | target/i386: remove old SSE decoder | Paolo Bonzini | 5 | -1907/+19 |
| 2022-10-18 | target/i386: move 3DNow to the new decoder | Paolo Bonzini | 6 | -76/+74 |
| 2022-10-18 | tests/tcg: extend SSE tests to AVX | Paolo Bonzini | 3 | -94/+112 |
| 2022-10-18 | target/i386: Enable AVX cpuid bits when using TCG | Paul Brook | 1 | -5/+5 |
| 2022-10-18 | target/i386: implement VLDMXCSR/VSTMXCSR | Paolo Bonzini | 2 | -0/+45 |
| 2022-10-18 | target/i386: implement XSAVE and XRSTOR of AVX registers | Paolo Bonzini | 1 | -3/+75 |
| 2022-10-18 | target/i386: reimplement 0x0f 0x28-0x2f, add AVX | Paolo Bonzini | 3 | -0/+185 |
| 2022-10-18 | target/i386: reimplement 0x0f 0x10-0x17, add AVX | Paolo Bonzini | 5 | -0/+264 |
| 2022-10-18 | target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX | Paolo Bonzini | 3 | -0/+81 |
| 2022-10-18 | target/i386: reimplement 0x0f 0x38, add AVX | Paolo Bonzini | 6 | -8/+524 |
| 2022-10-18 | target/i386: Use tcg gvec ops for pmovmskb | Richard Henderson | 1 | -5/+83 |
| 2022-10-18 | target/i386: reimplement 0x0f 0x3a, add AVX | Paolo Bonzini | 5 | -1/+491 |
| 2022-10-18 | target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes | Paolo Bonzini | 2 | -5/+5 |
| 2022-10-18 | target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX | Paolo Bonzini | 4 | -11/+122 |
| 2022-10-18 | target/i386: reimplement 0x0f 0x70-0x77, add AVX | Paolo Bonzini | 3 | -6/+293 |
