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2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)Philippe Mathieu-Daudé2-34/+9
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)Philippe Mathieu-Daudé2-158/+35
Convert 3-register operations to decodetree. Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), these instructions are not defined for the BYTE format. Therefore the TRANS_DF_iii_b() macro returns 'false' in that case, because no such instruction is decoded. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-22-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)Philippe Mathieu-Daudé2-12/+11
Convert 3-register operations to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Note, the format definition could be named @3rf_b (for 3R with a df field BYTE-based) but since the instruction class is named '3R', we simply call the format @3r to ease reviewing the msa.decode file. However we directly call the trans_msa_3rf() function, which handles the BYTE-based df field. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-21-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé2-176/+76
Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-20-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé2-39/+38
Convert 3-register floating-point or fixed-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-19-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé2-75/+31
Convert 3-register instructions with implicit data formats to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-18-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé2-75/+19
Convert 2-register operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-17-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé2-12/+21
Convert the FILL opcode (Vector Fill from GPR) to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé2-85/+53
Convert 2-register floating-point operations to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-15-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé2-59/+36
Convert load/store instructions to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-14-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé2-56/+27
Convert instructions with an 8-bit immediate value and either implicit data format or data format df to decodetree. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-13-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé2-17/+22
Convert the SHF opcode (Immediate Set Shuffle Elements) to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-12-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé2-97/+101
Convert instructions with an immediate bit index and data format df/m to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-11-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé2-77/+41
Convert instructions with a 5-bit immediate value to decodetree. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-10-f4bug@amsat.org>
2021-11-02target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé2-9/+21
Convert the LDI opcode (Immediate Load) to decodetree. Since it overlaps with the generic MSA handler, use a decodetree overlap group. Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-9-f4bug@amsat.org>
2021-11-02target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé2-18/+17
This 'shift amount' format is not always 16-bit, so name it generically as 'sa'. This will help to unify the various arg_msa decodetree generated structures. Rename the @bz format -> @bz_v (specific @bz with df=3) and @bz_df -> @bz (generic @bz). Since we modify &msa_bz, re-align its arguments, so the other structures added in the following commits stay visually aligned. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-8-f4bug@amsat.org>
2021-11-02target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé1-3/+3
Replace magic DataFormat value by the corresponding enum from CPUMIPSMSADataFormat. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-7-f4bug@amsat.org>
2021-11-02target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé1-7/+18
Have check_msa_access() return a boolean value so we can return early if MSA is not enabled (the instruction got decoded properly, but we raised an exception). Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-6-f4bug@amsat.org>
2021-11-02target/mips: Use dup_const() to simplifyPhilippe Mathieu-Daudé1-20/+3
The dup_const() helper makes the code easier to follow, use it. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-5-f4bug@amsat.org>
2021-11-02target/mips: Adjust style in msa_translate_init()Philippe Mathieu-Daudé1-1/+3
While the first 'off' variable assignment is unused, it helps to better understand the code logic. Move the assignation where it would have been used so it is easier to compare the MSA registers based on FPU ones versus the MSA specific registers. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211023214803.522078-34-f4bug@amsat.org>
2021-11-02target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé1-16/+16
The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-3-f4bug@amsat.org>
2021-11-02target/mips: Fix MSA MADDV.B opcodePhilippe Mathieu-Daudé1-16/+16
The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-2-f4bug@amsat.org>
2021-11-02MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardwarePhilippe Mathieu-Daudé1-3/+7
Hardware emulated models don't belong to the TCG MAINTAINERS section. Move them to a new 'Overall MIPS Machines' section in the 'MIPS Machines' group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211004092515.3819836-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02MAINTAINERS: Add entries to cover MIPS CPS / GIC hardwarePhilippe Mathieu-Daudé1-6/+14
MIPS CPS and GIC models are unrelated to the TCG frontend. Move them as new sections under the 'Devices' group. Cc: Paul Burton <paulburton@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211027041416.1237433-3-f4bug@amsat.org>
2021-11-02MAINTAINERS: Add MIPS general architecture support entryPhilippe Mathieu-Daudé1-1/+6
The architecture is covered in TCG (frontend and backend) and hardware models. Add a generic section matching the 'mips' word in patch subjects. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211004092515.3819836-2-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-20211101' ↵Richard Henderson4-0/+0
into staging qemu-openbios queue # gpg: Signature made Mon 01 Nov 2021 05:51:08 PM EDT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] * remotes/mcayland/tags/qemu-openbios-20211101: roms/openbios: update OpenBIOS images to b9062dea built from submodule Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02block-backend: Silence clang -m32 compiler warningHanna Reitz1-1/+1
Similarly to e7e588d432d31ecebc26358e47201dd108db964c, there is a warning in block/block-backend.c that qiov->size <= INT64_MAX is always true on machines where size_t is narrower than a uint64_t. In said commit, we silenced this warning by casting to uint64_t. The commit introducing this warning here (a93d81c84afa717b0a1a6947524d8d1fbfd6bbf5) anticipated it and so tried to address it the same way. However, it only did so in one of two places where this comparison occurs, and so we still need to fix up the other one. Fixes: a93d81c84afa717b0a1a6947524d8d1fbfd6bbf5 ("block-backend: convert blk_aio_ functions to int64_t bytes paramter") Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20211026090745.30800-1-hreitz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02linux-aio: add `dev_max_batch` parameter to laio_io_unplug()Stefano Garzarella3-5/+8
Between the submission of a request and the unplug, other devices with larger limits may have been queued new requests without flushing the batch. Using the new `dev_max_batch` parameter, laio_io_unplug() can check if the batch exceeds the device limit to flush the current batch. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20211026162346.253081-4-sgarzare@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02linux-aio: add `dev_max_batch` parameter to laio_co_submit()Stefano Garzarella3-10/+26
This new parameter can be used by block devices to limit the Linux AIO batch size more than the limit set by the AIO context. file-posix backend supports this, passing its `aio-max-batch` option previously added. Add an helper function to calculate the maximum batch size. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20211026162346.253081-3-sgarzare@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02file-posix: add `aio-max-batch` optionStefano Garzarella2-0/+16
Commit d7ddd0a161 ("linux-aio: limit the batch size using `aio-max-batch` parameter") added a way to limit the batch size of Linux AIO backend for the entire AIO context. The same AIO context can be shared by multiple devices, so latency-sensitive devices may want to limit the batch size even more to avoid increasing latency. For this reason we add the `aio-max-batch` option to the file backend, which will be used by the next commits to limit the size of batches including requests generated by this device. Suggested-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20211026162346.253081-2-sgarzare@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02block/export/fuse.c: fix musl buildFabrice Fontaine1-0/+4
Include linux/falloc.h if CONFIG_FALLOCATE_ZERO_RANGE is defined to fix https://gitlab.com/qemu-project/qemu/-/commit/50482fda98bd62e072c30b7ea73c985c4e9d9bbb and avoid the following build failure on musl: ../block/export/fuse.c: In function 'fuse_fallocate': ../block/export/fuse.c:643:21: error: 'FALLOC_FL_ZERO_RANGE' undeclared (first use in this function) 643 | else if (mode & FALLOC_FL_ZERO_RANGE) { | ^~~~~~~~~~~~~~~~~~~~ Fixes: - http://autobuild.buildroot.org/results/be24433a429fda681fb66698160132c1c99bc53b Fixes: 50482fda98b ("block/export/fuse.c: fix musl build") Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com> Message-Id: <20211022095209.1319671-1-fontaine.fabrice@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02ide: Cap LBA28 capacity announcement to 2^28-1Samuel Thibault1-2/+6
The LBA28 capacity (at offsets 60/61 of identification) is supposed to express the maximum size supported by LBA28 commands. If the device is larger than this, we have to cap it to 2^28-1. At least NetBSD happens to be using this value to determine whether to use LBA28 or LBA48 for its commands, using LBA28 for sectors that don't need LBA48. This commit thus fixes NetBSD access to disks larger than 128GiB. Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Message-Id: <20210824104344.3878849-1-samuel.thibault@ens-lyon.org> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02block/rbd: implement bdrv_co_block_statusPeter Lieven1-0/+112
the qemu rbd driver currently lacks support for bdrv_co_block_status. This results mainly in incorrect progress during block operations (e.g. qemu-img convert with an rbd image as source). This patch utilizes the rbd_diff_iterate2 call from librbd to detect allocated and unallocated (all zero areas). To avoid querying the ceph OSDs for the answer this is only done if the image has the fast-diff feature which depends on the object-map and exclusive-lock features. In this case it is guaranteed that the information is present in memory in the librbd client and thus very fast. If fast-diff is not available all areas are reported to be allocated which is the current behaviour if bdrv_co_block_status is not implemented. Signed-off-by: Peter Lieven <pl@kamp.de> Message-Id: <20211012152231.24868-1-pl@kamp.de> Reviewed-by: Ilya Dryomov <idryomov@gmail.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02block: Fail gracefully when blockdev-snapshot creates loopsKevin Wolf3-4/+70
Using blockdev-snapshot to append a node as an overlay to itself, or to any of its parents, causes crashes. Catch the condition and return an error for these cases instead. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1824363 Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20211018134714.48438-1-kwolf@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02block/file-posix: Fix return value translation for AIO discardsAri Sundholm1-2/+2
AIO discards regressed as a result of the following commit: 0dfc7af2 block/file-posix: Optimize for macOS When trying to run blkdiscard within a Linux guest, the request would fail, with some errors in dmesg: ---- [ snip ] ---- [ 4.010070] sd 2:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE [ 4.011061] sd 2:0:0:0: [sda] tag#0 Sense Key : Aborted Command [current] [ 4.011061] sd 2:0:0:0: [sda] tag#0 Add. Sense: I/O process terminated [ 4.011061] sd 2:0:0:0: [sda] tag#0 CDB: Unmap/Read sub-channel 42 00 00 00 00 00 00 00 18 00 [ 4.011061] blk_update_request: I/O error, dev sda, sector 0 ---- [ snip ] ---- This turns out to be a result of a flaw in changes to the error value translation logic in handle_aiocb_discard(). The default return value may be left untranslated in some configurations, and the wrong variable is used in one translation. Fix both issues. Fixes: 0dfc7af2b28 ("block/file-posix: Optimize for macOS") Cc: qemu-stable@nongnu.org Signed-off-by: Ari Sundholm <ari@tuxera.com> Signed-off-by: Emil Karlson <jkarlson@tuxera.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20211019110954.4170931-1-ari@tuxera.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2021-11-02block/vpc: Add a sanity check that fixed-size images have the right typeThomas Huth1-1/+2
The code in vpc.c uses BDRVVPCState->footer.type in various places to decide whether the image is a fixed-size (VHD_FIXED) or a dynamic (VHD_DYNAMIC) image. However, we never check that this field really contains VHD_FIXED if we detected a fixed size image in vpc_open(), so a wrong value here could cause quite some trouble during runtime. Suggested-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20211012082702.792259-1-thuth@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-11-02vmdk: allow specification of tools versionThomas Weißschuh2-4/+23
VMDK files support an attribute that represents the version of the guest tools that are installed on the disk. This attribute is used by vSphere before a machine has been started to determine if the VM has the guest tools installed. This is important when configuring "Operating system customizations" in vSphere, as it checks for the presence of the guest tools before allowing those customizations. Thus when the VM has not yet booted normally it would be impossible to customize it, therefore preventing a customized first-boot. The attribute should not hurt on disks that do not have the guest tools installed and indeed the VMware tools also unconditionally add this attribute. (Defaulting to the value "2147483647", as is done in this patch) Signed-off-by: Thomas Weißschuh <thomas.weissschuh.ext@zeiss.com> Message-Id: <20210913130419.13241-1-thomas.weissschuh.ext@zeiss.com> [hreitz: Added missing '#' in block-core.json] Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-11-02pylint: fix errors and warnings generated by tests/qemu-iotests/297Emanuele Giuseppe Esposito5-27/+29
Test 297 in tests/qemu-iotests currently fails: pylint has learned new things to check, or we simply missed them. All fixes in this patch are related to additional spaces used or wrong indentation. No functional change intended. Signed-off-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Message-Id: <20211008062821.1010967-2-eesposit@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-11-02qemu-img: Consistent docs for convert -FEric Blake2-2/+2
Use consistent capitalization, and fix a missed line (we duplicate the qemu-img synopses in too many places). Fixes: 1899bf4737 (qemu-img: Add -F shorthand to convert) Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20210921142812.2631605-1-eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-11-02Merge remote-tracking branch ↵Richard Henderson2-1/+25
'remotes/alex.williamson/tags/vfio-update-20211101.0' into staging VFIO update 2021-11-01 * Re-enable expanded sub-page BAR mappings after migration (Kunkun Jiang) * Trace dropped listener sections due to page alignment (Kunkun Jiang) # gpg: Signature made Mon 01 Nov 2021 03:48:28 PM EDT # gpg: using RSA key 42F6C04E540BD1A99E7B8A90239B9B6E3BB08B22 # gpg: issuer "alex.williamson@redhat.com" # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] * remotes/alex.williamson/tags/vfio-update-20211101.0: vfio/common: Add a trace point when a MMIO RAM section cannot be mapped vfio/pci: Add support for mmapping sub-page MMIO BARs after live migration Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02linux-user: Handle BUS_ADRALN in host_signal_handlerRichard Henderson1-0/+3
Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS si_codes to continue into the host-to-guest signal conversion code. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02tcg: Add helper_unaligned_{ld,st} for user-only sigbusRichard Henderson2-0/+16
To be called from tcg generated code on hosts that support unaligned accesses natively, in response to an access that is supposed to be aligned. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02accel/tcg: Report unaligned load/store for user-onlyRichard Henderson1-1/+6
Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02accel/tcg: Report unaligned atomics for user-onlyRichard Henderson1-1/+12
Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which has access to complete alignment info from the TCGMemOpIdx arg. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sparc: Set fault address in sparc_cpu_do_unaligned_accessRichard Henderson2-13/+20
We ought to have been recording the virtual address for reporting to the guest trap handler. Move the function to mmu_helper.c, so that we can re-use code shared with get_physical_address_data. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sparc: Split out build_sfsrRichard Henderson1-26/+46
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sparc: Remove DEBUG_UNALIGNEDRichard Henderson1-9/+0
The printf should have been qemu_log_mask, the parameters themselves no longer compile, and because this is placed before unwinding the PC is actively wrong. We get better (and correct) logging on the other side of raising the exception, in sparc_cpu_do_interrupt. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/sh4: Set fault address in superh_cpu_do_unaligned_accessRichard Henderson1-0/+5
We ought to have been recording the virtual address for reporting to the guest trap handler. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/s390x: Implement s390x_cpu_record_sigbusRichard Henderson3-10/+26
For s390x, the only unaligned accesses that are signaled are atomic, and we don't actually want to raise SIGBUS for those, but instead raise a SPECIFICATION error, which the kernel will report as SIGILL. Split out a do_unaligned_access function to share between the user-only s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02linux-user/ppc: Remove POWERPC_EXCP_ALIGN handlingRichard Henderson1-8/+0
We will raise SIGBUS directly from cpu_loop_exit_sigbus. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-14 21:10:31 +0000