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2016-06-07s390x/virtio-ccw: fix spellingMichael Tokarev1-1/+1
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-06-07Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell40-686/+737
pc, pci, virtio: new features, cleanups, fixes This includes some infrastructure for ipmi smbios tables. Beginning of acpi hotplug rework by Igor for supporting >255 CPUs. Misc cleanups and fixes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 07 Jun 2016 13:55:22 BST # gpg: using RSA key 0x281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" * remotes/mst/tags/for_upstream: (25 commits) virtio: move bi-endian target support to a single location pc-dimm: introduce realize callback pc-dimm: get memory region from ->get_memory_region() acpi: make bios_linker_loader_add_checksum() API offset based acpi: make bios_linker_loader_add_pointer() API offset based tpm: apci: cleanup TCPA table initialization acpi: cleanup bios_linker_loader_cleanup() acpi: simplify bios_linker API by removing redundant 'table' argument acpi: convert linker from GArray to BIOSLinker structure pc: use AcpiDeviceIfClass.send_event to issue GPE events acpi: extend ACPI interface to provide send_event hook pc: Postpone SMBIOS table installation to post machine init ipmi: rework the fwinfo to be fetched from the interface tests: acpi: update tables with consolidated legacy cpu-hotplug AML pc: acpi: cpuhp-legacy: switch ProcessorID to possible_cpus idx pc: acpi: simplify build_legacy_cpu_hotplug_aml() signature pc: acpi: consolidate legacy CPU hotplug in one file pc: acpi: mark current CPU hotplug functions as legacy pc: acpi: cpu-hotplug: make AML CPU_foo defines local to cpu_hotplug_acpi_table.c pc: acpi: consolidate \GPE._E02 with the rest of CPU hotplug AML ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-07docker: Don't use eval trick on MakefileEduardo Habkost1-2/+1
The eval trick for defining DOCKER_SRC_COPY doesn't do anything useful, as DOCKER_SRC_COPY is immediately expanded just after it is defined, and CUR_TIME is already defined using ":=". Simply define it using ":=" so it is evaluated only once. The eval trick was also triggering an weird error on Travis builds: qemu/tests/docker/Makefile.include:34: *** unterminated variable reference. Stop. The issue is not easily reproducible (maybe it's a bug in some versions of Make), but it is avoided if removing the eval trick. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-07virtio: move bi-endian target support to a single locationGreg Kurz4-9/+5
Paolo's recent cpu.h cleanups broke legacy virtio for ppc64 LE guests (and arm BE guests as well, even if I have not verified that). Especially, commit "33c11879fd42 qemu-common: push cpu.h inclusion out of qemu-common.h" has the side-effect of silently hiding the TARGET_IS_BIENDIAN macro from the virtio memory accessors, and thus fully disabling support of endian changing targets. To be sure this cannot happen again, let's gather all the bi-endian bits where they belong in include/hw/virtio/virtio-access.h. The changes in hw/virtio/vhost.c are safe because vhost_needs_vring_endian() is not called on a hot path and non bi-endian targets will return false anyway. While here, also rename TARGET_IS_BIENDIAN to be more precise: it is only for legacy virtio and bi-endian guests. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-07pc-dimm: introduce realize callbackXiao Guangrong2-0/+8
nvdimm needs to check if the backend memory is large enough to contain label data and init its memory region when the device is realized, so introduce realize callback which is called after common dimm has been realize Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-07pc-dimm: get memory region from ->get_memory_region()Xiao Guangrong2-2/+4
Curretly, the memory region of backed memory is all directly mapped to guest's address space, however, it will be not true for nvdimm device if we introduce nvdimm label which only can be indirectly accessed by ACPI DSM method Also it improves the comments a bit to reflect this fact Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-06-07acpi: make bios_linker_loader_add_checksum() API offset basedIgor Mammedov5-33/+22
It should help to make clear that bios_linker works in terms of offsets within a file. Also it should prevent mistakes where user passes as arguments pointers to unrelated to file blobs. While at it, considering that it's a ACPI checksum and it's initial value must be 0, move checksum field zeroing into bios_linker_loader_add_checksum() instead of doing it at every call site manually before bios_linker_loader_add_checksum() is called. In addition add extra boundary checks. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07acpi: make bios_linker_loader_add_pointer() API offset basedIgor Mammedov6-75/+83
cleanup bios_linker_loader_add_pointer() API by switching arguments to taking offsets relative to corresponding files instead of doing pointer arithmetic on behalf of user which were confusing. Also make offset inside of source file explicit in API so that user won't have to manually set it in destination file blob and while at it add additional boundary checks. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07tpm: apci: cleanup TCPA table initializationIgor Mammedov1-4/+1
At the time build_tpm_tcpa() is called the tcpalog size is always 0, so log_area_start_address which is actually offset from the start of ACPI_BUILD_TPMLOG_FILE is always 0. Also as 'TCPA' is allocated 0 filled, there is no point in calculating always 0 log_area_start_address and set tcpa->log_area_start_address to it since the field should always point to start of ACPI_BUILD_TPMLOG_FILE. Make code easier to read dropping not needed offset calculations. While at that move tcpalog allocation closer to the code that defines its size. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07acpi: cleanup bios_linker_loader_cleanup()Igor Mammedov3-7/+6
bios_linker_loader_cleanup() is called only from one place and returned value is immediately freed wich makes returning pointer from bios_linker_loader_cleanup() useless. Cleanup bios_linker_loader_cleanup() by freeing data there so that caller won't have to free it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07acpi: simplify bios_linker API by removing redundant 'table' argumentIgor Mammedov7-47/+93
'table' argument in bios_linker_add_foo() commands is a data blob of one of files also passed to the same API. So instead of passing blob in every API call, add and keep file name association with related blob at bios_linker_loader_alloc() time. And find blob by name looking up allocated file entries inside of bios_linker_add_foo() commands. It will: - make API less confusing, - enforce calling bios_linker_loader_alloc() before calling any bios_linker_add_foo() - make sure that blob is the correct one, i.e. associated with the right file name Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07acpi: convert linker from GArray to BIOSLinker structureIgor Mammedov8-58/+70
Patch just changes type of of linker variables to a structure, there aren't any functional changes. Converting linker to a structure will allow to extend it functionality in follow up patch adding sanity blob checks. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07pc: use AcpiDeviceIfClass.send_event to issue GPE eventsIgor Mammedov10-72/+50
it reduces number of args passed in handlers by 1 and a number of used proxy wrappers saving ~20LOC. Also it allows to make cpu/mem hotplug code more universal as it would allow ARM to reuse it without rewrite by providing its own send_event callback to trigger events usiong GPIO instead of GPE as fixed hadrware ACPI model doen't have GPE at all. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07acpi: extend ACPI interface to provide send_event hookIgor Mammedov6-9/+39
send_event() hook will allow to send ACPI event in a target specific way (GPE or GPIO based impl.) it will also simplify proxy wrappers in piix4pm/ich9 that access ACPI regs and SCI which are part of piix4pm/lcp_ich9 devices and call acpi_foo() API directly. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07pc: Postpone SMBIOS table installation to post machine initCorey Minyard1-2/+3
This is the same place that the ACPI SSDT table gets added, so that devices can add themselves to the SMBIOS table. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07ipmi: rework the fwinfo to be fetched from the interfaceCorey Minyard4-112/+109
Instead of scanning IPMI devices from a fwinfo list, allow the fwinfo to be fetched from the IPMI interface class. Then the code looking for IPMI fwinfo can scan devices on a bus and look for ones that implement the IPMI class. This will let the ACPI scope be defined by the calling code so the IPMI code doesn't have to know the scope. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07tests: acpi: update tables with consolidated legacy cpu-hotplug AMLIgor Mammedov4-0/+0
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07pc: acpi: cpuhp-legacy: switch ProcessorID to possible_cpus idxIgor Mammedov2-11/+14
In legacy cpu-hotplug ProcessorID == APIC ID is used in MADT and cpu-hotplug AML. It was fine as both are 8bit and unique. Spec depricated Processor() with corresponding ProcessorID and advises to use Device() and UID instead of it. However UID is just 32bit and it can't fit ARM's arch_id(MPIDR) which is 64bit. Also in case of sparse arch_id() distribution, managment/lookup of maps by arch_id(APIC ID/MPIDR) becomes complex and expensive. In preparation to common CPU hotplug with ARM and to simplify lookup in possible_cpus[] map switch ProcessorID to possible_cpus index in MADT. Legacy cpu-hotplug considerations: HW interface of it is APIC ID based bitmask so it's impossible to change, also CPON package in AML also APIC ID based as well all the methods. To avoid massive rewrite of AML keep is so and just break assumption that ProcessorID == APIC ID, ammending CPU_MAT_METHOD to accept APIC ID and possible_cpus index, it needs them both to patch MADT entry template. Also switch to possible_cpus index Processor(ProcessorID) AML. That way changes to MADT/AML are minimal and kept inside AML/MADT not affecting external interfaces. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07pc: acpi: simplify build_legacy_cpu_hotplug_aml() signatureIgor Mammedov3-8/+5
since IO block used by CPU hotplug is fixed size and initialized it the same file as build_legacy_cpu_hotplug_aml() just use ACPI_GPE_PROC_LEN directly instead of passing it around in several files. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07pc: acpi: consolidate legacy CPU hotplug in one fileIgor Mammedov3-250/+233
Since AML part of CPU hotplug is tightly coupled with its hardware part (IO port layout/protocol), move build_legacy_cpu_hotplug_aml() to cpu_hotplug.c and remove empty cpu_hotplug_acpi_table.c Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07pc: acpi: mark current CPU hotplug functions as legacyIgor Mammedov6-19/+21
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07pc: acpi: cpu-hotplug: make AML CPU_foo defines local to ↵Igor Mammedov2-7/+7
cpu_hotplug_acpi_table.c now as those defines are used only locally inside of cpu_hotplug_acpi_table.c, move them out of header file. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07pc: acpi: consolidate \GPE._E02 with the rest of CPU hotplug AMLIgor Mammedov2-4/+4
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07pc: acpi: consolidate CPU hotplug AMLIgor Mammedov3-113/+106
move the former SSDT part of CPU hoplug close to DSDT part. AML is only moved but there isn't any functional change. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-06-07pc: acpi: remove AML for empty/not used GPE handlersIgor Mammedov1-17/+0
ACPI spec requires GPE handlers only for GPE events that hardware implements. So remove AML for not supported by QEMU device model events. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07acpi: add aml_refof()Igor Mammedov2-0/+9
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07acpi: add aml_debug()Igor Mammedov2-0/+10
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07tests: acpi: report names of expected files in verbose modeIgor Mammedov1-5/+13
print expected file name if it doesn't exists if verbose mode is enabled*. It helps to avoid running bios-tables-test under debugger to figure out missing file name. *) verbose mode is enabled if "V" env. variable is set Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
2016-06-07Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160607' ↵Peter Maydell21-127/+388
into staging ppc patch queue for 2016-05-31 Latest patch queue for ppc. Several significant things in here: * A bunch of patches from BenH fixing things in TCG - This should fix several regressions introduced by recent patches for better HV mode support - It also fixes some other bugs discovered along the way * Some fixes and cleanups for Mac machine types from Marc Cave-Ayland * Preliminary patches towards dynamic DMA window support from Alexey Kardashevskiy - This includes a patch to migration code code * Increase number of hotpluggable memory slots - Includes a change to KVM generic code, ACKed by Paolo * Another TCG fix for an SPE instruction # gpg: Signature made Tue 07 Jun 2016 11:46:57 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160607: (26 commits) ppc: Do not take exceptions on unknown SPRs in privileged mode ppc: Add missing slbfee. instruction on ppc64 BookS processors ppc: Fix slbia decode ppc: Fix mtmsr decoding ppc: POWER7 has lq/stq instructions and stq need to check ISA ppc: POWER7 had ACOP and PID registers ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors ppc: Properly tag the translation cache based on MMU mode dbdma: use DMA memory interface for memory accesses macio: use DMA memory interface for non-block ATAPI transfers target-ppc: fixup bitrot in mmu_helper.c debug statements spapr_pci: Drop cannot_instantiate_with_device_add_yet=false ppc: fix hrfid, tlbia and slbia privilege ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV ppc: Better figure out if processor has HV mode spapr: Introduce pseries-2.7 machine type spapr: Increase hotpluggable memory slots to 256 spapr_pci: Add and export DMA resetting helper spapr_pci: Reset DMA config on PHB reset ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-07ppc: Do not take exceptions on unknown SPRs in privileged modeBenjamin Herrenschmidt1-2/+9
The architecture specifies that mtspr/mfspr on an unknown SPR number should act as a nop in privileged mode. I haven't removed the warning however as it can be useful for diagnosing. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Add missing slbfee. instruction on ppc64 BookS processorsBenjamin Herrenschmidt3-0/+57
Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix slbia decodeBenjamin Herrenschmidt1-1/+1
Since at least the 2.05 architecture, the slbia instruction takes an IH field in the opcode to provide some control on the effect of the slbia on the ERATs (level-1 TLB). We can safely ignore it as we always flush the whole qemu TLB but we should allow the bits in the decode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix mtmsr decodingBenjamin Herrenschmidt1-1/+1
We had code to handle the L bit in the opcode but we didn't allow it in the decode mask. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: POWER7 has lq/stq instructions and stq need to check ISABenjamin Herrenschmidt2-2/+5
The PPC_64BX instruction flag is used for a couple of newer instructions currently on POWER8 but our implementation for them works for POWER7 too (and already does the proper checking of what is permitted) with one exception: stq needs to check the ISA version. This fixes the latter and add the instructions to POWER7 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: POWER7 had ACOP and PID registersBenjamin Herrenschmidt1-0/+18
We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash modeBenjamin Herrenschmidt4-44/+31
This ports the existing 64-bit mechanism to 32-bit, thus series of 64 tlbie's followed by a sync like some versions of Darwin (ab)use will result in a single flush. We apply a pending flush on any sync instruction though, as Darwin doesn't use tlbsync on non-SMP systems. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processorsBenjamin Herrenschmidt1-0/+8
The processor only uses some bits of the address and invalidates an entire congruence class. Some OSes such as Darwin and HelenOS take advantage of this and occasionally invalidate the entire TLB by just doing a series of 64 consecutive tlbie for example. Our code tries to be too smart here only invalidating a segment congruence class (ie, allowing more address bits to be relevant in the invalidation), this fails miserably on those OSes. Instead don't bother, do like ppc64 and blow the whole tlb when tlbie is executed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Properly tag the translation cache based on MMU modeBenjamin Herrenschmidt1-1/+1
We used to always flush the TLB when changing relocation mode in MSR:IR and MSR:DR (ie. MMU on/off for Instructions and Data). We don't anymore since we have split mmu_idx for instruction and data. However, since we hard code the mmu_idx in the translated code, we now need to also make sure MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings. Darwin gets hurt by this problem. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07dbdma: use DMA memory interface for memory accessesMark Cave-Ayland1-6/+7
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07macio: use DMA memory interface for non-block ATAPI transfersMark Cave-Ayland1-1/+2
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07target-ppc: fixup bitrot in mmu_helper.c debug statementsMark Cave-Ayland1-14/+24
This fixes compilation of mmu_helper.c when all of the debug #defines at the start of the file are enabled. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07spapr_pci: Drop cannot_instantiate_with_device_add_yet=falseMarkus Armbruster1-1/+0
It's become redundant since it was added in commit 09aa9a5 "spapr-pci: enable adding PHB via -device". Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: fix hrfid, tlbia and slbia privilegeCédric Le Goater1-3/+3
commit 74693da98894 ('ppc: tlbie, tlbia and tlbisync are HV only') introduced some extra checks on the instruction privilege. slbia was changed wrongly and hrfid, tlbia were forgotten. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVBenjamin Herrenschmidt2-4/+8
This helper is only used by the various instructions that can alter MSR and not interrupts. Add a comment to that effect to the interrupt code as well in case somebody wants to change this Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07ppc: Better figure out if processor has HV modeBenjamin Herrenschmidt3-5/+22
We use an env. flag which is set to the initial value of MSR_HVB in the msr_mask. We also adjust the POWER8 mask to set SHV. Also use this to adjust ctx.hv so that it is *set* when the processor doesn't have an HV mode (970 with Apple mode for example), thus enabling hypervisor instructions/SPRs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: ctx.hv used to be defined only for the hypervisor kernel (HV=1|PR=0). It is now defined also when PR=1 and conditions are fixed accordingly. stripped unwanted tabs.] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07spapr: Introduce pseries-2.7 machine typeBharata B Rao1-2/+20
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07spapr: Increase hotpluggable memory slots to 256Bharata B Rao1-2/+12
KVM now supports 512 memslots on PowerPC (earlier it was 32). Allow half of it (256) to be used as hotpluggable memory slots. Instead of hard coding the max value, use the KVM supplied value if KVM is enabled. Otherwise resort to the default value of 32. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07spapr_pci: Add and export DMA resetting helperAlexey Kardashevskiy2-2/+10
This will be later used by the "ibm,reset-pe-dma-window" RTAS handler which resets the DMA configuration to the defaults. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07spapr_pci: Reset DMA config on PHB resetAlexey Kardashevskiy1-6/+11
LoPAPR dictates that during system reset all DMA windows must be removed and the default DMA32 window must be created so does the patch. At the moment there is just one window supported so no change in behaviour is expected. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-07spapr_iommu: Add root memory regionAlexey Kardashevskiy3-7/+14
We are going to have multiple DMA windows at different offsets on a PCI bus. For the sake of migration, we will have as many TCE table objects pre-created as many windows supported. So we need a way to map windows dynamically onto a PCI bus when migration of a table is completed but at this stage a TCE table object does not have access to a PHB to ask it to map a DMA window backed by just migrated TCE table. This adds a "root" memory region (UINT64_MAX long) to the TCE object. This new region is mapped on a PCI bus with enabled overlapping as there will be one root MR per TCE table, each of them mapped at 0. The actual IOMMU memory region is a subregion of the root region and a TCE table enables/disables this subregion and maps it at the specific offset inside the root MR which is 1:1 mapping of a PCI address space. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.1 at 2025-01-18 05:59:01 +0000